MEMORY CELLS HAVING A FOLDED DIGIT LINE ARCHITECTURE
Memory arrays having folded architectures and methods of making the same. Specifically, memory arrays having a portion of the transistors in a row that are reciprocated and shifted with respect to other transistors in the same row. Trenches formed between the rows may form a weave pattern throughout the array, in a direction of the row. Trenches formed between legs of the transistors may also form a weave pattern throughout the array in a direction of the row.
1 . A memory device, comprising:
a plurality of memory cells arranged in a grid pattern comprising a plurality of rows and columns;
a plurality of column isolation trenches, wherein each of the column isolation trenches is arranged between adjacent columns of the plurality of memory cells, wherein each of the column isolation trenches is linear throughout an entire length of the plurality of columns; and
a plurality of row isolation trenches, wherein each of the row isolation trenches is arranged between adjacent rows of the plurality of memory cells, and wherein each of the plurality of row isolation trenches is non-linear throughout an entire length of the plurality of rows.
2 . The memory device, as set forth in claim 1 , wherein each of the plurality of memory cells comprises a transistor comprising:
a first leg having a drain formed therein;
a second leg having a source formed therein;
an inter-leg trench formed between the first leg and the second leg; and
a channel formed under the trench.
3 . The memory device, as set forth in claim 2 , wherein the inter-leg trench of each transistor in a respective row of the plurality of rows is non-linear throughout the entire length of the plurality of rows.
4 . The memory device, as set forth in claim 3 , wherein a non-linear pattern of the inter-leg trench is substantially the same as a non-linear pattern of the plurality of row isolation trenches.
5 . The memory device, as set forth in claim 2 , wherein each transistor comprises a fin field effect transistors (finFET).
6 . The memory device, as set forth in claim 2 , wherein each first leg has a width approximately equal to ½ F and each second leg has a width approximately equal to ½ F.
7 . The memory device, as set forth in claim 2 , wherein each inter-leg trench has a width approximately equal to 1½ F.
8 . The memory device, as set forth in claim 1 , wherein the non-linear row isolation trenches form a weave pattern comprising a single weave pattern.
9 . The memory device, as set forth in claim 1 , wherein the non-linear row isolation trenches form a weave pattern comprising a double weave pattern.
10 . The memory device, as set forth in claim 1 , wherein the non-linear row isolation trenches form a weave pattern comprising that is greater than a double weave pattern.
11 . A memory device, comprising:
an array of finFETs arranged in a plurality of rows and columns, wherein each of the finFETs comprises a first leg, a second leg, and a shallow trench formed therebetween, and wherein at least one finFET in a row of the array is shifted with respect to at least another finFET in the row, in a direction parallel to the columns.
12 . The memory device, as set forth in claim 11 , wherein each finFET in a row of the array is shifted with respect to at least one finFET in the row, arranged directly adjacent to the at least one finFET.
13 . The memory device, as set forth in claim 11 , comprising a plurality of digit lines formed in a direction parallel to the plurality of rows, such that each of the plurality of digit lines is electrically coupled to either the first leg or the second leg of a finFET in every other column.
14 . The memory device, as set forth in claim 11 , comprising a plurality of digit lines formed in a direction parallel to the plurality of rows, such that each of the plurality of digit lines is electrically coupled to either the first leg or the second leg of a portion, but not all of the finFETs in a respective row.
15 . The memory device, as set forth in claim 11 , comprising a plurality of digit lines formed in a direction parallel to the plurality of rows, and a plurality of word lines formed in a direction parallel to the plurality of columns, wherein the plurality of word lines is formed adjacent to and in contact with the finFETs, and wherein the plurality of digit lines is formed in a plane above the finFETs and the word lines.
16 . The memory device, as set forth in claim 11 , wherein at least one finFET in a row of the array is reciprocated with respect to at least another finFET in the row.
17 . The memory device, as set forth in claim 11 , wherein each of the finFETs in a row of the array is separated from the finFETs in an adjacent row by a row isolation trench that forms a weave pattern in a direction of the row.
18 . The memory device, as set forth in claim 11 , wherein the shallow trenches of each of the finFETs in a row of the array forms a weave pattern in a direction of the row.
19 . A memory device, comprising:
an array of memory cells arranged in a plurality of rows and columns, wherein at least one memory cell in a row of the array is shifted with respect to at least another memory cell in the row, in a direction parallel to the columns;
a plurality of column isolation trenches, wherein each of the column isolation trenches is arranged between adjacent columns of the array of memory cells, wherein each of the column isolation trenches is linear throughout an entire length of the plurality of columns; and
a plurality of row isolation trenches, wherein each of the row isolation trenches is arranged between adjacent rows of the array of memory cells, and wherein each of the plurality of row isolation trenches is non-linear throughout an entire length of the plurality of rows.
20 . The memory device, as set forth in claim 19 , wherein the array of memory cells comprises and array of finFETs.
21 . The memory device, as set forth in claim 20 , wherein each of the finFETs comprises a first leg, a second leg, and a shallow trench formed therebetween.
22 . The memory device, as set forth in claim 21 , comprising a plurality of digit lines formed in a direction parallel to the plurality of rows, such that each of the plurality of digit lines is electrically coupled to either the first leg or the second leg of a finFET in every other column.
23 . The memory device, as set forth in claim 21 , comprising a plurality of digit lines formed in a direction parallel to the plurality of rows, such that each of the plurality of digit lines is electrically coupled to either the first leg or the second leg of a portion, but not all of the finFETs in a respective row.
24 . The memory device, as set forth in claim 21 , wherein the shallow trenches of each of the finFETs in a row of the array forms a non-linear pattern in a direction of the row.
25 . The memory device, as set forth in claim 19 , comprising a plurality of digit lines formed in a direction parallel to the plurality of rows, and a plurality of word lines formed in a direction parallel to the plurality of columns, wherein the plurality of word lines is formed adjacent to and in contact with the memory cells, and wherein the plurality of digit lines is formed in a plane above the memory cells and the word lines.
26 . The memory device, as set forth in claim 19 , wherein at least one memory cell in a row of the array is reciprocated with respect to at least another memory cell in the row.
27 . The memory device, as set forth in claim 19 , wherein each memory cell in a row of the array is shifted with respect to at least one memory cell in the row, arranged directly adjacent to the at least one memory cell.