50 Gb/s Ethernet using serializer/deserializer lanes
View Patent ↗Systems, devices, and methods of implementing 50 Gb/s Ethernet using serializer/deserializer lanes are disclosed. One such device includes circuitry operable to provide a media access control (MAC) interface. The MAC interface is associated with a port having a 50 Gb/s link rate. The device also includes circuitry operable to generate Ethernet frames from data received at the MAC interface and circuitry operable to distribute the Ethernet frames across a group of serial/deserializer (SERDES) lanes associated with the port, the group having size N. The device also includes circuitry operable to transmit the distributed Ethernet frames on each of the SERDES lanes at a 50/N Gb/s rate.
1. A device comprising:
circuitry configured to
function as a media access control (MAC) interface associated with a port having an M Gb/s link rate, M being a value greater than or equal to 10;
generate Ethernet frames from data received at the MAC interface;
distribute the Ethernet frames across a group of serializer/deserializer (SERDES) lanes associated with the port, the group having a size N which is greater than 1; and
transmit the distributed Ethernet frames on each of the SERDES lanes at an M/N Gb/s rate.
2. The device of claim 1 , wherein the circuitry is configured to:
receive Ethernet frames on each of the SERDES lanes at a M/N Gb/s rate;
bond the SERDES lanes into a stream of received Ethernet frames; and
provide data from the bonded stream of Ethernet frames to the MAC port at an M Gb/s rate.
3. The device of claim 1 , wherein
M is 50.
4. The device of claim 1 , wherein
N is 2or 4.
5. The device of claim 1 , wherein
the SERDES lanes are arranged to electrically couple to a corresponding plurality of SERDES lanes on a midplane of a blade server chassis.
6. The device of claim 5 , wherein
each of the SERDES lanes on the midplane is associated with an electrical trace group on the midplane.
7. The device of claim 6 , wherein
each of electrical trace group includes a transmit differential pair and a receive differential pair.
8. The device of claim 1 , wherein
the circuitry is configured to distribute the Ethernet frames across the N SERDES lanes using Multi-Lane Distribution across a plurality of Physical Coding Sublayer (PCS) lanes.
9. The device of claim 1 , wherein
the device is configured to support another link rate lower than M Gb/s and to autonegotiate between the link rates.
10. The device of claim 9 , wherein
the autonegotiation is conducted on a lane 0 of the SERDES lanes.
11. The device of claim 9 , wherein
the autonegotiation is conducted in accordance with IEEE 802.3an.
12. A device comprising:
a Media Access Control (MAC) interface associated with an M Gb/s port and configured to generate Ethernet frames from data received at the MAC interface, M being a value greater than or equal to 10;
a group of serializer/deserializer (SERDES) lanes associated with the port, the group having a size N which is greater than 1; and
a physical layer transceiver (PHY) configured to distribute the Ethernet frames across the group of SERDES lanes, wherein
the SERDES lanes are each configured to transmit distributed Ethernet frames at a M/N Gb/s rate.
13. The device of claim 12 , wherein
M is 50.
14. The device of claim 12 , wherein
N is 2or 4.
15. The device of claim 12 , wherein
the SERDES lanes reside in the PHY.
16. The device of claim 12 , wherein
at least a first SERDES lane of the group of SERDES lanes is arranged to electrically couple to a corresponding at least first SERDES lane on a midplane of a blade server chassis and at least a second SERDES lane of the group of SERDES lanes is arranged to electrically couple to a corresponding at least second SERDES lane on the midplane.
17. The device of claim 12 , wherein
each of the SERDES lanes are arranged to electrically couple to a corresponding plurality of SERDES lanes on a midplane of a blade server chassis.
18. The device of claim 17 , wherein
each of the SERDES lanes on the midplane are associated with an electrical trace group on the midplane.
19. The device of claim 12 , wherein
N=2and the PHY is further configured to distribute the Ethernet frames over 4 virtual lanes, and
the device further comprises a 2:1 bit level multiplexer configured to multiplex the 4 virtual lanes across the 2 SERDES lanes.
20. A device comprising:
circuitry configured to
generate Ethernet frames from data received at a media access control (MAC) interface associated with a port having a 50 Gb/s link rate;
distribute the Ethernet frames across a plurality of serializer/deserializer (SERDES) lanes associated with the port; and
transmit the distributed Ethernet frames on each of the SERDES lanes at a 50/N Gb/s rate, where N is the number of the plurality of SERDES lanes.