IP Library Granted Patent US 9,442,615
Granted Patent B2
US 9,442,615 · App. 14/503,068 · Granted Sep 13, 2016

Frequency shifting for simultaneous active matrix display update and in-cell capacitive touch

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Quick Facts
Patent No.
US 9,442,615
App. No.
14/503,068
Granted
Sep 13, 2016
Kind
B2
Abstract

Embodiments generally provide a method, input device, and processing system for frequency shifting for synchronized display updating and capacitive sensing. The method includes driving a display signal onto at least one display electrode for updating a display. The method further includes driving a first capacitive sensing signal having a first frequency onto at least one sensor electrode, wherein the first frequency is synchronized to the display signal. The method further includes driving a second capacitive sensing signal having a second frequency onto the at least one sensor electrode, wherein the first and second frequencies differ and a timing of the display signal is adjusted to maintain synchronization with the second frequency, and wherein each capacitive sensing signal and the display signal are driven in parallel for at least some period of time.

Claims (38)

1. An input device comprising:

a plurality of display electrodes;

a plurality of sensor electrodes; and

a processing system coupled with the plurality of display electrodes and with the plurality of sensor electrodes, wherein the processing system is configured to:

drive a display signal onto at least one of the plurality of display electrodes for updating pixels of a display,

drive, during a first period that at least partially overlaps with driving the display signal for updating pixels of the display, a first capacitive sensing signal having a first frequency onto at least one sensor electrode of the plurality of sensor electrodes, wherein the first frequency is synchronized with the display signal, and

drive, during a second period that at least partially overlaps with driving the display signal for updating pixels of the display, a second capacitive sensing signal having a second frequency onto the at least one sensor electrode, wherein the first and second frequencies differ; and

adjusting a timing of the display signal to maintain synchronization of the display signal with the second frequency.

2. The input device of claim 1 , wherein the timing of the display signal is further adjusted to maintain synchronization with a phase of the second capacitive sensing signal, wherein the phase of the second capacitive sensing signal is different from a phase of the first capacitive sensing signal.

3. The input device of claim 1 , wherein each of the first and second capacitive sensing signals defines a respective one or more sensing cycles, each sensing cycle comprising two half cycles, wherein a duration of each half cycle of the two half cycles is synchronized with the display signal.

4. The input device of claim 1 , wherein adjusting a timing of the display signal includes adjusting a line rate for a gate line used to activate a row of display pixels of the display.

5. The input device of claim 4 , wherein the difference between the first and second frequencies results from varying an amount of time between display updates of sub-pixels in the activated row.

6. The input device of claim 4 , wherein adjusting a timing of the display signal includes delaying a turn-on time for the gate line.

7. The input device of claim 1 , wherein the processing system further comprises a display line buffer having a size based on a length of a capacitive sensing period associated with driving the first and second capacitive sensing signals, the size of the buffer further based on a difference in a host pixel update rate and a display pixel update rate.

8. The input device of claim 1 , wherein at least one of the plurality of sensor electrodes comprises at least one of the plurality of display electrodes.

9. A processing system, comprising:

a display module configured to drive a display signal onto at least one of a plurality of display electrodes for updating pixels of a display; and

a sensing module configured to:

drive, during a first period that at least partially overlaps with driving the display signal for updating pixels of the display, a first capacitive sensing signal having a first frequency onto at least one sensor electrode of the plurality of sensor electrodes, wherein the first frequency is synchronized with the display signal, and

drive, during a second period that at least partially overlaps with driving the display signal for updating pixels of the display, a second capacitive sensing signal having a second frequency onto the at least one sensor electrode, wherein the first and second frequencies differ,

wherein the display module is further configured to adjust a timing of the display signal to maintain synchronization of the display signal with the second frequency.

10. The processing system of claim 9 , wherein each of the first and second capacitive sensing signals defines a respective one or more sensing cycles, each sensing cycle comprising two half cycles, wherein a duration of each cycle of the two half cycles is synchronized with the display signal.

11. The processing system of claim 9 , wherein adjusting a timing of the display signal includes adjusting a line rate for a gate line used to activate a row of pixels of the display.

12. The processing system of claim 11 , wherein the difference between the first and second frequencies results from varying an amount of time between display updates of sub-pixels in the activated row.

13. The processing system of claim 11 , wherein adjusting a timing of the display signal includes delaying a turn-on time for the gate line.

14. The processing system of claim 9 , wherein the processing system further comprises a display line buffer having a size based on a length of a capacitive sensing period associated with driving the first and second capacitive sensing signals, the size of the buffer further based on a difference in a host pixel update rate and a display pixel update rate.

15. The processing system of claim 9 , wherein at least one of the plurality of sensor electrodes comprises at least one of the plurality of display electrodes.

16. A method, comprising:

driving a display signal onto at least one of a plurality of display electrodes for updating pixels of a display,

driving, during a first period that at least partially overlaps with driving the display signal for updating pixels of the display, a first capacitive sensing signal having a first frequency onto at least one sensor electrode of a plurality of sensor electrodes, wherein the first frequency is synchronized with the display signal, and

driving, during a second period that at least partially overlaps with driving the display signal for updating pixels of the display, a second capacitive sensing signal having a second frequency onto the at least one sensor electrode, wherein the first and second frequencies differ; and

adjusting a timing of the display signal to maintain synchronization of the display signal with the second frequency.

17. The method of claim 16 , wherein each of the first and second capacitive sensing signals defines a respective one or more sensing cycles, each sensing cycle comprising two half cycles, wherein a duration of each half cycle of the two half cycles is synchronized with the display signal.

18. The method of claim 16 , wherein adjusting a timing of the display signal includes adjusting a line rate for a gate line used to activate a row of pixels of the display.

19. The method of claim 18 , wherein the difference between the first and second frequencies results from varying an amount of time between display updates of sub-pixels in the activated row.

20. The method of claim 18 , wherein adjusting a timing of the display signal includes delaying a turn-on time for the gate line.

21. The method of claim 16 , wherein adjusting the timing of the display signal is performed using a display line buffer having a size based on a length of a capacitive sensing period associated with driving the first and second capacitive sensing signals, the size of the buffer further based on a difference in a host pixel update rate and a display pixel update rate.

22. The method of claim 16 , wherein at least one of the plurality of sensor electrodes comprises at least one of the plurality of display electrodes.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 5, 2021
From: CREATIVE LEGEND SEMICONDUCTOR (HONG KONG) LIMITED
To: OMNIVISION TDDI ONTARIO LIMITED PARTNERSHIP
Reel/Frame 058035/0823 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 21, 2020
From: SYNAPTICS INCORPORATED
To: CREATIVE LEGEND SEMICONDUCTOR (HONG KONG) LIMITED
Reel/Frame 052457/0740 →
RELEASE OF SECURITY INTEREST Recorded Apr 20, 2020
From: WELLS FARGO BANK, NATIONAL ASSOCIATION
To: SYNAPTICS INCORPORATED
Reel/Frame 052441/0289 →
SECURITY INTEREST Recorded Sep 27, 2017
From: SYNAPTICS INCORPORATED
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 044037/0896 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2016
From: REYNOLDS, JOSEPH KURTH
To: SYNAPTICS INCORPORATED
Reel/Frame 037906/0016 →