High speed communication jack
A high speed communication jack including a housing including a port for accepting a plug, the port including a plurality of pins each connected to a corresponding signal line in the plug and a shielding case surrounding the housing. A flexible circuit board between the shielding case and the housing having a substrate, a plurality of vias extending through the substrate with each via being configured to accommodate a pin on the housing, a plurality of traces on a first side of the substrate, with each trace extending from a corresponding one of the plurality of vias, and a shielding plane on a second side of the substrate opposite the first side of the substrate.
1. A method of producing a high speed communication jack including the steps of:
forming a housing including a port for accepting a plug, the port including a plurality of pins each connected to a corresponding signal line in the plug;
forming a shielding case surrounding the housing;
forming a flexible circuit board between the shielding case and the housing including the steps of;
forming a substrate,
forming a plurality of vias extending through the substrate with each via being configured to accommodate a pin on the housing,
forming a plurality of traces on a first side of the substrate, with each trace extending from a corresponding one of the plurality of vias,
adjusting the height, width, length and spacing of at least two traces such that the impedance of the at least two traces are substantially the same; and
forming a shielding plane on a second side of the substrate opposite the first side of the substrate.
2. The method of claim 1 wherein the height of the at least two matched traces is between approximately 2 mils and approximately 6 mils.
3. The method of claim 1 wherein the spacing between the at least two matched traces is between approximately 3 mils and approximately 10 mils.
4. The method of claim 1 , wherein each trace is formed with a first portion and a second portion.
5. The method of claim 4 , wherein the width of each trace is adjusted in the first portion.
6. The method of claim 4 , wherein the width of each trace is adjusted in the second portion.
7. The method of claim 4 , wherein the width of each trace is adjusted in the first portion and the second portion.
8. The method of claim 1 wherein a common mode filter is formed between two matched traces and the via of each trace and at least one layer in the substrate between the trace and the shielding layer form a capacitor.
9. The method of claim 8 wherein the size of the capacitor is determined by the distance from the trace to the at least one layer.
10. The method of claim 8 wherein the capacitor is sized between approximately 1 picofarad (pf) and 5 pf.
11. A high speed communication jack including:
a housing including a port for accepting a plug, the port including a plurality of pins each connected to a corresponding signal line in the plug;
a shielding case surrounding the housing;
a flexible circuit board between the shielding case and the housing having
a substrate,
a plurality of vias extending through the substrate with each via being configured to accommodate a pin on the housing,
a plurality of traces on a first side of the substrate, with each trace extending from a corresponding one of the plurality of vias; and
a shielding plane on a second side of the substrate opposite the first side of the substrate,
wherein,
the height, width, length and spacing of at least two traces are adjusted such that the impedance of the at least two traces are substantially the same.
12. The jack of claim 11 wherein the height of the at least two matched traces is between approximately 2 mils and approximately 6 mils.
13. The jack of claim 11 , wherein the spacing between the at least two matched traces is between approximately 3 mils and approximately 10 mils.
14. The jack of claim 11 , wherein each trace is formed with a first portion and a second portion.
15. The jack of claim 14 , wherein the width of each trace is adjusted in the first portion.
16. The jack of claim 14 , wherein the width of each trace is adjusted in the second portion.
17. The jack of claim 14 , wherein the width of each trace is adjusted in the first portion and the second portion.
18. The jack of claim 11 including a common mode filter formed between two matched traces where the via of each trace and at least one layer in the substrate between the trace and the shielding layer.
19. The jack of claim 18 wherein the size of capacitor is determined by the distance from the trace to the at least one layer.
20. The jack of claim 18 wherein the capacitors are sized between approximately 1 picofarad (pf) and 5 pf.