IP Library › Granted Patent US 9,496,271
Granted Patent B2
US 9,496,271 · App. 14/506,160 · Granted Nov 15, 2016

3DIC system with a two stable state memory and back-bias region

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Quick Facts
Patent No.
US 9,496,271
App. No.
14/506,160
Granted
Nov 15, 2016
Kind
B2
Abstract

A 3D IC based system, including: a first layer including first transistors; a second layer overlying the first layer, the second layer includes a plurality of second transistors, where the second layer includes at least one through second layer via having a diameter of less than 400 nm, and where at least one of the plurality of second transistors forms a two stable state memory cell including a back-bias region.

Claims (49)

1. A 3D IC based system, comprising:

a first layer comprising first transistors;

a second layer overlying said first layer, said second layer comprises a plurality of second transistors,

wherein said second layer comprises at least one through second layer via having a diameter of less than 400 nm, and

wherein at least one of said plurality of second transistors forms a two stable state memory cell comprising a back-bias region.

2. A 3D IC based system according to claim 1 ,

wherein said back-bias region is disposed to one side of a channel region of said second transistors.

3. A 3D IC based system according to claim 1 ,

wherein at least one of said second transistors comprise a side gate on one side and said back-bias region on the opposite side of a channel region.

4. A 3D IC based system according to claim 1 ,

wherein said back-bias region comprises polysilicon.

5. A 3D IC based system according to claim 1 ,

wherein at least one of said plurality of second transistors and one of said first transistors share a back-bias region.

6. A 3D IC based system according to claim 1 ,

wherein at least two of said plurality of second transistors are connected by a common doped mono-crystalline structure.

7. A 3D IC based system according to claim 1 ,

wherein a first portion of at least one of said first transistors is self-aligned to a second portion of at least one of said plurality of second transistors.

8. A 3D IC based system, comprising:

a first layer comprising first transistors;

a second layer overlying said first layer, said second layer comprises a plurality of second transistors,

wherein said second layer thickness is less than 400 nm, and

wherein at least one of said plurality of second transistors forms a two stable state memory cell comprising a back-bias region.

9. A 3D IC based system according to claim 8 ,

wherein said back-bias region is disposed to one side of a channel region of said second transistors.

10. A 3D IC based system according to claim 8 ,

wherein at least one of said second transistors comprise a side gate on one side and said back-bias region on the opposite side of a channel region.

11. A 3D IC based system according to claim 8 ,

wherein said back-bias region comprises polysilicon.

12. A 3D IC based system according to claim 8 ,

wherein at least one of said plurality of second transistors and one of said first transistors share a back-bias region.

13. A 3D IC based system according to claim 8 ,

wherein at least two of said plurality of second transistors are connected by a common doped mono-crystalline structure.

14. A 3D IC based system according to claim 8 ,

wherein a first portion of at least one of said first transistors is self-aligned to a second portion of at least one of said plurality of second transistors.

15. A 3D IC based system, comprising:

a first layer comprising first transistors;

a second layer overlying said first layer, said second layer comprises a plurality of second transistors,

wherein a first portion of at least one of said first transistors is self-aligned to a second portion of at least one of said plurality of second transistors, and

wherein at least one of said plurality of second transistors forms a two stable state memory cell comprising a back-bias region.

16. A 3D IC based system according to claim 15 ,

wherein said back-bias region is disposed to one side of said of a channel region of second transistors.

17. A 3D IC based system according to claim 15 ,

wherein at least one of said second transistors comprise a side gate on one side and said back-bias region on the opposite side of a channel region.

18. A 3D IC based system according to claim 15 ,

wherein said back-bias region comprises polysilicon.

19. A 3D IC based system according to claim 15 ,

wherein at least one of said plurality of second transistors and one of said first transistors share a back-bias region.

20. A 3D IC based system according to claim 15 ,

wherein at least two of said plurality of second transistors are connected by a common doped mono crystal structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 13, 2014
From: OR-BACH, ZVI; WIDJAJA, YUNIARTO
To: MONOLITHIC 3D INC.
Reel/Frame 033938/0816 →