A layer system having a layer region, whereby the layer region has a single-crystal silicon substrate with a front side and a back side, and whereby a textured surface is formed on the front side and the textured surface has a topography with different heights and a thin film layer of a metal oxide and/or an oxide ceramic is formed on the textured surface, whereby the thin film layer covers the textured surface only partially.
1. A layer system having a layer region, the layer region comprising:
a single-crystal silicon substrate with a front side and a back side;
a textured surface formed on the front side, the textured surface having a topography with different heights; and
a thin film layer of a metal oxide and/or an oxide ceramic formed on the textured surface, the thin film layer formed such that a top portion of exposed peaks or plateaus is not covered by the thin film layer, the thin film layer disposed between adjacent exposed peaks or plateaus,
wherein the adjacent exposed peaks or plateaus are higher than a flat surface of the thin film layer, the flat surface being substantially parallel to the back side of the substrate.
2. The layer system according to claim 1 , wherein the textured surface has a pyramid-shaped topography.
3. The layer system according to claim 1 , wherein exposed peaks with no thin film and/or plateaus with no thin film project above the flat surface of the thin film layer.
4. The layer system according to claim 1 , wherein the thin film layer comprises a catalyst.
5. The layer system according to claim 4 , wherein the catalyst has platinum and/or palladium and/or rhodium.
6. The layer system according to claim 1 , wherein the thin film layer has a thickness smaller than 10 μm.
7. The layer system according to claim 1 , wherein a metallically conductive intermediate layer partially or completely covers the textured surface between the thin film layer and the textured surface.
8. The layer system according to claim 7 , wherein the metallically conductive intermediate layer comprises a silicide layer.
9. The layer system according to claim 8 , wherein the silicide layer comprises platinum and/or titanium and/or palladium.
10. The layer system according to claim 7 , wherein the metallically conductive intermediate layer is electrically connectable.
11. The layer system according to claim 1 , wherein the thin film layer is electrically connectable.
12. The layer system according to claim 1 , wherein the textured silicon substrate has a p- or an n-type doping in the layer region.
13. The layer system according to claim 1 , wherein the layer region is integrated in an SGFET or CCFET gas sensor as a gas-sensitive control electrode.
14. The layer system according to claim 2 , wherein side surfaces of the pyramid-shaped topography are 111 surfaces and the textured surface on a top side has 100 surfaces.
15. The layer system according to claim 1 , wherein the thin film layer contains gallium oxide and/or tin oxide and/or barium titanate and/or barium carbonate.
16. The layer system according to claim 7 , wherein the textured surface contains pyramid top surfaces or pyramid peaks and a distance of 1 μm to 10 μm is formed between directly adjacent pyramid peaks or pyramid top surfaces and the pyramid top surfaces or pyramid peaks are between 1 μm and 10 μm in height.
17. The layer system according to claim 7 , wherein the metallic intermediate layer has a texturing with a texture spacing of 0.1 μm to 1 μm and a texture depth of 0.1 μm to 1 μm and the texture spacing and the texture depth are in each case smaller than those at the surface of the silicon substrate.
18. The layer system according to claim 1 , wherein the thin film layer is formed polycrystalline and the grain sizes of the thin film layer are smaller than 2 μm.
19. The layer system according to claim 1 , wherein peaks and raised plateaus of the textured surface are spaced apart at different intervals, and wherein some peaks or plateaus are covered by the thin film layer.
20. The layer system according to claim 1 , wherein the textured surface contains pyramid top surfaces or pyramid peaks with bases that overlap, and wherein some of the pyramid top surfaces or pyramid peaks are covered by the thin film layer.
21. The layer system according to claim 1 , wherein the thin film layer is disposed on a lower portion of the exposed peaks or plateaus.
22. A layered structure having a layer region, the layer region comprising:
a single-crystal silicon substrate with a front side and a back side;
a textured surface formed on the front side, the textured surface having a topography with different heights; and
a thin film layer of a metal oxide and/or an oxide ceramic formed on the textured surface, the thin film layer covering the textured surface only partially,
wherein a metallically conductive intermediate layer partially or completely covers the textured surface between the thin film layer and the textured surface, and
wherein the metallic intermediate layer has a texturing with a texture spacing of 0.1 μm to 1 μm and a texture depth of 0.1 μm to 1 μm and the texture spacing and the texture depth are in each case smaller than those at the surface of the silicon substrate.