Processor branch cache with secondary branches
A processor uses a prediction unit to predict subsequent instructions of a program to be executed by the processor. Many implementations or combinations of implementations may be used to predict the subsequent instruction of the program. In one embodiment, a branch cache is used to store branch information. A prediction table is used to store prediction information based on the branch. A prediction logic module determines whether a branch is taken or not taken based on the branch information stored in the branch cache and the prediction information stored in the prediction table.
1. An integrated circuit comprising:
a branch cache that stores, in a single branch cache entry, branch information about a primary branch and a secondary branch, the branch information including a branch target address for the primary branch in an instruction fetch block and an address offset of the secondary branch in the instruction fetch block; and
a branch prediction logic module that calculates a branch target address for the secondary branch in the instruction fetch block based on the address offset of the secondary branch and a predicted branch direction of the secondary branch.
2. The integrated circuit of claim 1 , wherein the branch cache is comprised of two cache banks.
3. The integrated circuit of claim 1 , wherein the secondary branch is a conditional branch.
4. The integrated circuit of claim 1 , wherein the secondary branch is not associated with a delay slot.
5. The integrated circuit of claim 1 , wherein the branch prediction logic module calculates the predicted branch direction of the secondary branch based on prediction information associated with the secondary branch stored in a prediction table.
6. The integrated circuit of claim 1 , wherein the prediction logic module calculates the branch target address for the secondary branch based on the address offset of the secondary branch and a program counter value.
7. A non-transitory computer readable medium storing instructions that when executed by a processor generate a representation of an electronic circuit, the electronic circuit comprising:
a branch cache that stores, in a single branch cache entry, branch information about a primary branch and a secondary branch, the branch information including a branch target address for the primary branch in an instruction fetch block and an address offset of the secondary branch in the instruction fetch block; and
a branch prediction logic module that calculates a branch target address for the secondary branch in the instruction fetch block based on the branch target address offset of the secondary branch and a predicted branch direction of the secondary branch.
8. The non-transitory computer readable medium of claim 7 , wherein the branch cache is comprised of two cache banks.
9. The non-transitory computer readable medium of claim 7 , wherein the secondary branch is a conditional branch.
10. The non-transitory computer readable medium of claim 7 , wherein the secondary branch is not associated with a delay slot.
11. The non-transitory computer readable medium of claim 7 , wherein the generated branch prediction logic module calculates the predicted branch direction of the secondary branch based on prediction information associated with the secondary branch stored in a prediction table.
12. The non-transitory computer readable medium of claim 7 , wherein the generated prediction logic module calculates the branch target address for the secondary branch based on the address offset of the secondary branch and a program counter value.
13. A method comprising:
retrieving a secondary information associated with a secondary branch stored in a branch cache entry of a branch cache, the branch cache entry comprising branch cache information associated with a primary branch and the secondary branch, the secondary branch information including an address offset associated with the secondary branch; and
determining, by a processor, a branch target address associated with the secondary branch based on the address offset associated with the secondary branch and a predicted branch direction of the secondary branch.
14. The method of claim 13 , wherein the branch cache is comprised of two cache banks.
15. The method of claim 13 , wherein the secondary branch is a conditional branch.
16. The method of claim 13 , wherein the secondary branch is not associated with a delay slot.
17. The method of claim 13 , wherein the predicted branch direction of the secondary branch is based on prediction information associated with the secondary branch stored in a prediction table.
18. The method of claim 13 , wherein the branch target address for the secondary branch is based on the address offset of the secondary branch and a program counter value.