Memory card and host device thereof
A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal.
1. A host device couplable to a storage device, comprising:
a command line;
a plurality of data lines;
a clock line; and
a controller coupled to the command line, the data lines and the clock line, wherein:
the controller is configured to send a clock signal through the clock line;
the controller is configured to send data and receive a first response through the data lines, in accordance with a single edge transfer based on either one of a rise edge and a fall edge of the clock signal, in a first transfer mode;
the controller is configured to send data and receive a first response through the data lines, in accordance with a double edge transfer based on both the rise edge and the fall edge of the clock signal, in a second transfer mode;
the controller is configured to send a first command and receive a second response through the command line, in accordance with the single edge transfer;
the controller is configured to switch between the first transfer mode and the second transfer mode after sending the first command;
the controller is configured to perform the double edge transfer through the data lines simultaneously with the single edge transfer through the command line;
the controller is configured to send a second command and receive a third response through the command line, in accordance with the single edge transfer;
the controller is configured to send the second command of the command line while transferring data of the data lines, the second command being used for informing the storage device that the host device stops transferring data of the data lines; and
a transfer rate of the double edge transfer is higher than a transfer rate of the single edge transfer.
2. The host device according to claim 1 , wherein:
the controller is configured to send a third command and receive a fourth response through the command line, in accordance with either one of the rise edge and the fall edge of the clock signal; and
the controller is configured to receive first status data that includes information indicating that the storage device supports the second transfer mode, through the data lines in response to the third command.
3. The host device according to claim 1 , wherein the controller is configured to receive second status data that includes information indicating that the storage device is set into the second transfer mode, through the data lines in response to the first command.
4. The host device according to claim 2 , wherein:
the first status data includes data fields of a plurality of function groups; and
the second transfer mode is assigned to one of the function groups.
5. The host device according to claim 4 , wherein the number of the function groups is six.
6. The host device according to claim 2 , wherein the first status data further includes information on a maximum consumption current required for the second transfer mode.
7. The host device according to claim 2 , wherein:
the controller is configured to send data through the data lines, in accordance with the clock signal having a first frequency, in a normal bus mode;
the controller is configured to send data through the data lines, in accordance with the clock signal having a second frequency, in a high-speed bus mode;
the second frequency is higher than the first frequency; and
the first status data further includes information indicating that the storage device supports the high-speed bus mode.
8. The host device according to claim 2 , wherein:
the first status data further includes information indicating that the storage device supports an IC card function; and
the controller is configured to validate the IC card function of the storage device in response to the first status data.
9. The host device according to claim 2 , wherein the first status data further includes information on a command system.
10. The host device according to claim 1 , wherein:
the controller is configured to receive data in a plurality of data blocks through the data lines; and
a CRC code is added to each of the data blocks.
11. The host device according to claim 1 , wherein:
the controller is configured to send data through all data lines in a first bit mode; and
the controller is configured to send data through only one of the data lines in a second bit mode.
12. The host device according to claim 1 , wherein the storage device is a semiconductor memory.
13. The host device according to claim 12 , wherein the semiconductor memory is a NAND flash memory.