IP Library Granted Patent US 9,262,963
Granted Patent B2
US 9,262,963 · App. 14/508,639 · Granted Feb 16, 2016

Display unit and electronic apparatus

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Quick Facts
Patent No.
US 9,262,963
App. No.
14/508,639
Granted
Feb 16, 2016
Kind
B2
Abstract

A display unit provided with a display panel including a light emitting element and a pixel circuit for each pixel, and a drive circuit configured to drive each of the pixels. The pixel circuit includes: a first transistor configured to sample a voltage corresponding to a picture signal, the first transistor having characteristics that a parasitic capacitance at a time when the first transistor is turned off is decreased as magnitude of negative bias applied to a gate voltage is increased; a second transistor configured to control a current flowing through the light emitting element based on magnitude of the voltage sampled by the first transistor; and a retention capacitance configured to retain the voltage sampled by the first transistor.

Claims (16)

1. A display unit provided with a display panel including a light emitting element and a pixel circuit for each pixel, and a drive circuit configured to drive each of the pixels, the pixel circuit comprising:

a first transistor configured to sample a voltage corresponding to a picture signal, the first transistor having characteristics that a parasitic capacitance at a time when the first transistor is turned off is decreased as magnitude of negative bias applied to a gate voltage is increased;

a second transistor configured to control a current flowing through the light emitting element based on magnitude of the voltage sampled by the first transistor; and

a retention capacitance configured to retain the voltage sampled by the first transistor.

2. The display unit according to claim 1 , wherein

the drive circuit applies a first voltage to a gate of the first transistor when the light emitting element is allowed to emit light, the first voltage having a negative value allowing the first transistor to be turned off.

3. The display unit according to claim 2 , wherein

the first voltage is lower than a second voltage, the second voltage being applied to the gate of the first transistor to turn off the first transistor during non-light emission of the light emitting element.

4. The display unit according to claim 2 , wherein

the drive circuit changes a voltage applied to the gate of the first transistor from the first voltage to a third voltage until the light emitting element is allowed to be turned off, the third voltage being higher than the first voltage.

5. The display unit according to claim 2 , wherein the first transistor is a top-gate type transistor including an oxide semiconductor layer.

6. The display unit according to claim 5 , wherein the first transistor has the gate at a position facing the oxide semiconductor layer, and a low-resistance source region and a low-resistance drain region that are formed in the oxide semiconductor layer by treating the oxide semiconductor layer with use of the gate as a mask.

7. An electronic apparatus provided with a display unit, the display unit including a display panel that includes a light emitting element and a pixel circuit for each pixel, and a drive circuit configured to drive each of the pixels, the pixel circuit comprising:

a first transistor configured to sample a voltage corresponding to a picture signal, the first transistor having characteristics that a parasitic capacitance at a time when the first transistor is turned off is decreased as magnitude of negative bias applied to a gate voltage is increased;

a second transistor configured to control a current flowing through the light emitting element based on magnitude of the voltage sampled by the first transistor; and

a retention capacitance configured to retain the voltage sampled by the first transistor.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2015
From: SONY CORPORATION
To: JOLED INC.
Reel/Frame 036090/0968 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 7, 2014
From: TOYOMURA, NAOBUMI
To: SONY CORPORATION
Reel/Frame 033904/0968 →