Semiconductor apparatus
According to one embodiment, a semiconductor apparatus divides each of a first area in which a first transistor is formed and a second area in which a second transistor is formed into two or more areas, and alternately arranges the divided areas of the first area and the second area. Further, the semiconductor apparatus according to one embodiment configures the second area to have a total area larger than that of the first area or to have the number of divisions greater than that of the first area. Furthermore, in the semiconductor apparatus according to one embodiment, a gate pad of the first transistor and a gate pad of the second transistor are provided in the second area.
1. A semiconductor apparatus comprising:
a first area, a first transistor being formed in two or more divided areas of the first area; and
a second area, a second transistor being formed in two or more divided areas of the second area, wherein
a total area of the second area is larger than a total area of the first area,
the divided areas of the first area and the second area are alternately arranged, and
the gate pad of the first transistor and the gate pad of the second transistor are formed in the second area.
2. The semiconductor apparatus according to claim 1 , wherein
a gate line of the first transistor is formed continuously across the divided first area that is connected to the gate pad of the first transistor, and
a gate line of the second transistor is formed continuously across the second area that is connected to the gate pad of the second transistor.
3. The semiconductor apparatus according to claim 1 , wherein
the first transistor and the second transistor are trench transistors, and
a current flowing from a source of the first transistor is output from a source of the second transistor via a substrate area of the semiconductor apparatus.
4. The semiconductor apparatus according to claim 1 , wherein
the number of areas of the second area is greater than the number of areas of the first area, and
the total number of the number of divisions of the first area and the number of divisions of the second area is five or greater.
5. The semiconductor apparatus according to claim 1 , wherein
a first source pad that is connected to a source of the first transistor is formed in the first area,
a second source pad that is connected to a source of the second transistor is formed in the second area, and
a total area of the second source pad is larger than a total area of the first source pad or the number of the second source pads is greater than the number of the first source pads.
6. The semiconductor apparatus according to claim 5 , wherein
the first source pad and the second source pad have continuous shapes in each of the divided areas.
7. The semiconductor apparatus according to claim 1 , wherein
the gate pad of the first transistor and the gate pad of the second transistor are arranged along a contour of the semiconductor chip on which the first transistor and the second transistor are formed.
8. The semiconductor apparatus according to claim 7 , wherein
the second area includes a plurality of source pad sequences in which source pads of the second transistor are continuously arranged, and
the gate pad of the first transistor and the gate pad of the second transistor are disposed in the same source pad sequence among the plurality of source pad sequences.
9. The semiconductor apparatus according to claim 7 , wherein
the gate pad of the first transistor and the gate pad of the second transistor are arranged diagonally on the semiconductor chip.
10. The semiconductor apparatus according to claim 7 , wherein
the second area includes a plurality of source pad sequences in which the source pads of the second transistor are consecutively arranged, and
the gate pad of the first transistor and the gate pad of the second transistor are disposed in different source pad sequences from each other among the plurality of source pad sequences.
11. The semiconductor apparatus according to claim 1 , wherein
trench gate electrodes that are connected to the respective gate pads are formed in the first area and the second area, and
the trench gate electrode formed in the first area and the trench gate electrode formed in the second area are formed to extend in directions that are orthogonal to each other.
12. The semiconductor apparatus according to claim 1 , further comprising:
a gate line of the first transistor, the gate line comprising a polygonal shape where the gate pad is formed.
13. The semiconductor apparatus according to claim 1 , further comprising:
a back-metal layer on a second plane, the second plane being opposed to a first plane where the gate pad is provided among planes of the semiconductor chip on which the first transistor and the second transistor are formed.
14. A semiconductor apparatus comprising:
a first area, a first transistor being formed in two or more divided areas of the first area; and
a second area, a second transistor being formed in two or more divided areas of the second area, wherein
the number of areas of the second area is greater than the number of areas of the first area,
the divided areas of the first area and the second area are alternately arranged, and
the gate pad of the first transistor and the gate pad of the second transistor are formed in the second area.
15. The semiconductor apparatus according to claim 14 , wherein
a gate line of the first transistor is formed continuously across the divided first area that is connected to the gate pad of the first transistor, and
a gate line of the second transistor is formed continuously across the divided second area that is connected to the gate pad of the second transistor.
16. The semiconductor apparatus according to claim 14 , wherein
the first transistor and the second transistor are trench transistors, and
a current flowing from a source of the first transistor is output from a source of the second transistor via a substrate area of the semiconductor apparatus.
17. The semiconductor apparatus according to claim 14 , wherein
a total area of the second area is larger than a total area of the first area, and
the total number of the number of divisions of the first area and the number of divisions of the second area is five or greater.
18. A method of manufacturing a semiconductor apparatus comprising:
setting a first area on a semiconductor chip, the first area being divided into two or more areas,
setting a second area on the semiconductor chip, a total area of the second area being larger than a total area of the first area, the second area being divided into two or more areas, and the divided areas of the first area and the second area are alternately arranged;
forming a first transistor in the first area;
forming a second transistor in the second area; and
forming a gate pad of the first transistor and a gate pad of the second transistor in the second area.
19. The semiconductor apparatus according to claim 1 , further comprising:
a semiconductor substrate of a first conductivity-type;
a metal layer formed on a back surface of the semiconductor substrate;
an epitaxial layer formed on a front surface of the semiconductor substrate;
a second conductivity-type diffusion layer formed on the epitaxial layer; and
a first conductivity-type diffusion layer formed on the second conductivity-type diffusion layer,
wherein the first and second transistors comprise vertical transistors which are formed in a trench formed in the first conductivity-type diffusion layer, the second conductivity-type diffusion layer and the epitaxial layer.
20. The semiconductor apparatus according to claim 1 , further comprising:
a plurality of first source pads that are formed in the first area and connected to a source of the first transistor; and
a first gate line of the first transistor, which is formed in the first area and surrounds the plurality of first source pads, and comprises:
a pair of long sections;
a pair of short sections which connect the ends of the pair of long sections; and
an extended portion which extends from a long section of the plurality of long sections, into the second area and connects to the gate pad of the first transistor.