IP Library Granted Patent US 9,709,335
Granted Patent B2
US 9,709,335 · App. 14/510,122 · Granted Jul 18, 2017

Dispatch control method for furnace process

Inventors: Jyun-Da Wu (Taoyuan County, TW); Shih-Tsung Hsiao (Hsinchu, TW); Chien-Chung Chen (Hsinchu, TW)
Assignee: Powerchip Technology Corporation
F27D19/00G05B19/418H01L21/67253H01L21/67778G05B2219/45031G05B2219/45132Y02P90/20
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,709,335
App. No.
14/510,122
Granted
Jul 18, 2017
Kind
B2
Abstract

A dispatch control method for a furnace process including the following steps is provided. Before a plurality of lots of wafers is loaded into a furnace, the characteristic variation value of each of the plurality of lots of wafers is calculated. The plurality of lots of wafers is ordered according to the size of the characteristic variation values. The plurality of lots of wafers is placed in the furnace in a descending order of the characteristic variation values corresponding to a plurality of locations in the furnace causing the characteristic variation values to change from smaller to larger.

Claims (77)

1. A dispatch control method for a furnace process, comprising:

calculating a characteristic variation value of each of a plurality of lots of wafers before the plurality of lots of wafers is loaded into a furnace;

ordering the plurality of lots of wafers according to a size of the characteristic variation values; and

placing the plurality of lots of wafers in the furnace in a descending order of the characteristic variation values corresponding to a plurality of locations in the furnace causing the characteristic variation values to change from smaller to larger.

2. The method of claim 1 , further comprising defining a characteristic parameter value related to a product before the plurality of lots of wafers is loaded into the furnace.

3. The method of claim 2 , wherein the characteristic parameter value comprises a threshold voltage, a saturation current, or a resistance value.

4. The method of claim 1 , wherein the characteristic variation values are calculated from a function of the characteristic variation values, and the function of the characteristic variation values is related to at least one of a gate length and a thickness of a residual silicon oxide used for forming a source and a drain.

5. The method of claim 1 , further comprising performing a selection on the ordered plurality of lots of wafers.

6. The method of claim 5 , wherein a method of performing the selection on the plurality of lots of wafers comprises performing the selection on the ordered plurality of lots of wafers according to an average lot size interval.

7. The method of claim 5 , wherein a method of performing the selection on the plurality of lots of wafers comprises providing a lot number to each of the ordered plurality of lots of wafers in order, and selecting the lot number by rounding a value calculated according to the following formula:

Lot

number

=

1

+

[

(

Total

lot

size

of

a

pluraqlity

of

lots

of

wafers

-

1

)

×

N

Maximum

lot

size

of

a

batch

-

1

]

wherein N is an integer of at least 0, and a maximum value of N is one less than a maximum lot size of a batch.

8. The method of claim 1 , wherein the characteristic variation values of the plurality of lots of wafers are calculated via an advanced process control system.

9. The method of claim 1 , wherein a placement location of each of the plurality of lots of wafers in a batch in the furnace is decided via a dispatch system.

10. The method of claim 1 , wherein a dispatch of the plurality of lots of wafers is executed via a manufacturing execution system.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2019
From: POWERCHIP TECHNOLOGY CORPORATION
To: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 049770/0160 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 16, 2014
From: WU, JYUN-DA; HSIAO, SHIH-TSUNG; CHEN, CHIEN-CHUNG
To: POWERCHIP TECHNOLOGY CORPORATION
Reel/Frame 033958/0197 →
Priority Claims (1)
TW 103125690 A · Jul 28, 2014 · national
Continuity (1)
Related Publication 20160025414A1 · Jan 28, 2016