IP Library Granted Patent US 9,269,765
Granted Patent B2
US 9,269,765 · App. 14/510,125 · Granted Feb 23, 2016

Semiconductor device having gate wire disposed on roughened field insulating film

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Quick Facts
Patent No.
US 9,269,765
App. No.
14/510,125
Granted
Feb 23, 2016
Kind
B2
Abstract

A semiconductor device of the present disclosure includes a semiconductor layer provided on a main surface of a substrate. A cell region is provided with a gate insulating film disposed on the semiconductor layer and a gate electrode disposed on the gate insulating film, and a wiring region is provided with a field insulating film disposed on the semiconductor layer and a gate wire disposed on the field insulating film. An end of the field insulating film has a convex shape in a cross section perpendicular to the main surface of the substrate, and an upper surface of the field insulating film is rougher than an upper surface of a portion of the gate wire below which the field insulating film is not disposed.

Claims (27)

1. A semiconductor device comprising:

a substrate on which a cell region and a wiring region are defined;

a semiconductor layer disposed on a main surface of the substrate;

a gate insulating film disposed on the semiconductor layer in the cell region;

a gate electrode disposed on the gate insulating film;

a field insulating film disposed on the semiconductor layer in the wiring region; and

a gate wire partially disposed on the field insulating film and electrically connected to the gate electrode,

wherein the field insulating film is thicker than the gate insulating film;

an end of the field insulating film has a convex shape in a cross section perpendicular to the main surface of the substrate; and

an upper surface of the field insulating film is rougher than an upper surface of a portion of the gate wire below which the field insulating film is not disposed.

2. The semiconductor device according to claim 1 , wherein the upper surface of the field insulating film has a centerline average roughness within a range of 0.025 μm to 0.1 μm.

3. The semiconductor device according to claim 1 ,

wherein the field insulating film includes:

a first insulating film disposed on the semiconductor layer and composed of polysilicon; and

a second insulating film disposed on the first insulating film and composed of silicon oxide.

4. The semiconductor device according to claim 1 ,

wherein in the cross section perpendicular to the main surface of the substrate,

an angle formed by the upper surface of the semiconductor layer and a tangent line to the upper surface of the field insulating film at a point where the upper surface of the field insulating film is in contact with the semiconductor layer is 80° or more and less than 90°; and

an angle formed by a center line of the upper surface of the field insulating film and a tangent line to the upper surface of the field insulating film at a point where the upper surface of the field insulating film in the end of the field insulating film crosses the center line is 5° or more and 30° or less.

5. The semiconductor device according to claim 1 , wherein the gate electrode and the gate wire are composed of polysilicon.

6. The semiconductor device according to claim 1 , wherein the semiconductor layer is composed of silicon carbide.

7. The semiconductor device according to claim 1 , wherein the thickness of the field insulating film is 3 to 6 times more than the thickness of the gate insulating film.

8. The semiconductor device according to claim 3 , wherein the thickness of the second insulating film of the field insulating film is 4 to 6 times more than the thickness of the gate insulating film.

9. The semiconductor device according to claim 1 ,

wherein the semiconductor layer includes, in the wiring region, a first impurity region of a first conductivity type and a second impurity region of a second conductivity type that is disposed on the first impurity region;

the gate insulating film is disposed between the second impurity region and the portion of the gate wire below which the field insulating film is not disposed; and

in the cross section perpendicular to the main surface of the substrate, the thickness D 1 of the second impurity region below the field insulating film and the thickness D 2 of the second impurity region below the gate insulating film have the relation of D 1 >D 2 .

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 18, 2015
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 035045/0413 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2014
From: KUDOU, CHIAKI
To: PANASONIC CORPORATION
Reel/Frame 033977/0587 →