Content addressable memory cells, memory arrays and methods of forming the same

1. A content addressable memory cell comprising:

a first transistor disposed in a first transistor layer above a substrate;

a second transistor disposed in a second transistor layer above the first transistor layer, the second transistor coupled to the first transistor;

a third transistor disposed in a third transistor layer above the second transistor layer, the third transistor coupled to the second transistor; and

a memory element disposed in a memory element layer above the substrate, the memory element coupled to the first transistor and the second transistor,

wherein the content addressable memory cell comprises a minimum feature size F, and an area of between 18F 2 and 36F 2 .

2. The content addressable memory cell of claim 1 , wherein each of the transistors comprises a vertically-oriented pillar-shaped transistor.

3. The content addressable memory cell of claim 1 , wherein each of the transistors comprises a field-effect transistor or a bipolar transistor.

4. The content addressable memory cell of claim 1 , wherein:

the content addressable memory cell comprises a plurality of memory elements disposed in the memory element layer; and

each of the memory elements comprises a reversible resistance-switching memory element.

5. The content addressable memory cell of claim 4 , wherein each of the memory elements comprises one or more of a metal oxide, a solid electrolyte, a phase-change material, a magnetic material, and a carbon material.

6. The content addressable memory cell of claim 4 , wherein each of the memory elements comprises one or more of NiO, Nb 2 O 5 , TiO 2 , HfO 2 , Al 2 O 3 , MgO x , CrO 2 , VO, BN, TaO 2 , Ta 2 O 3 , and AlN.

7. A content addressable memory array comprising a plurality of content addressable memory cells of claim 1 .

8. A method of forming a content addressable memory cell, the method comprising:

forming a first transistor in a first transistor layer above a substrate;

forming a second transistor in a second transistor layer above the first transistor layer;

coupling the second transistor to the first transistor;

forming a third transistor in a third transistor layer above the second transistor layer;

coupling the third transistor to the second transistor;

forming a memory element in a memory element layer above the substrate; and

coupling the memory element to the first transistor and the second transistor,

wherein the content addressable memory cell comprises a minimum feature size F, and an area of between 18F 2 and 36F 2 .

9. The method of claim 8 , wherein each of the transistors comprises a vertically-oriented pillar-shaped transistor.

10. The method of claim 8 , wherein each of the transistors comprises a field-effect transistor or a bipolar transistor.

11. The method of claim 8 , wherein the memory element comprises a reversible resistance-switching memory element.