IP Library Granted Patent US 9,285,815
Granted Patent B2
US 9,285,815 · App. 14/513,879 · Granted Mar 15, 2016

Power supply integrated circuit with feedback control

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Quick Facts
Patent No.
US 9,285,815
App. No.
14/513,879
Granted
Mar 15, 2016
Kind
B2
Abstract

Power regulator circuitry that can provide a regulated power signal. The power regulator circuitry may include data processing circuitry configured to determine the regulated power signal to arbitrate power supply requirements of first and second powered devices according to power supply information associated with the first and second powered devices. The power regulator circuitry may also include output circuitry configured to output the regulated power signal to one or both of the first and second powered devices.

Claims (30)

1. Power regulator circuitry, comprising:

communication interface circuitry configured to receive power supply information, the power supply information including power source information associated with a plurality of power sources external to the power regulator circuitry;

data processing circuitry configured to determine a regulated power signal to arbitrate power supply requirements of first and second powered devices according to the power supply information and a weighted averaged load between the first and second powered devices based on priority information of the first and second powered devices, the power supply information also including powered device information associated with the first and second powered devices; and

output circuitry configured to output the regulated power signal to one or both of the first and second powered devices.

2. The power regulator circuitry of claim 1 , wherein the data processing circuitry is further configured to determine the regulated power signal according to load information associated with the first and second powered devices.

3. The power regulator circuitry of claim 1 , wherein the data processing circuitry is further configured to determine the regulated power signal according to priority information of the first and second powered devices.

4. The power regulator circuitry of claim 1 , wherein the data processing circuitry is further configured to determine the regulated power signal according to information indicating that the first powered device has a highest priority, and wherein the power regulator circuitry is further configured to determine the regulated power signal according to power supply information solely associated with the first powered device instead of other powered devices, including the second powered device.

5. The power regulator circuitry of claim 1 , wherein the regulated power signal is associated with supplied electrical power.

6. The power regulator circuitry of claim 1 , wherein the power supply information is received from the first and second powered devices.

7. The power regulator circuitry of claim 1 , wherein the output circuitry is further configured to receive the power supply information from first and second power supply devices, wherein the power supply information includes information on a first supplied electrical power supplied by the first power supply device and on a second supplied electrical power supplied by the second power supply device, and wherein the regulated power signal is associated with one or both of the first and second supplied electrical powers.

8. A method, comprising:

receiving, at power management circuitry, a plurality of respective power signals from a plurality of power supply devices external to the power management circuitry;

receiving, at the power management circuitry, power supply information, the power supply information including power source information associated with the plurality of power supply devices; and

arbitrating, by the power management circuitry, the plurality of respective power signals between a plurality of powered devices according to the power supply information and a weighted averaged load between the plurality of powered devices, the weighted averaged load based on priority information of the plurality of powered devices, and the power supply information also including powered device information associated with the plurality of powered devices.

9. The method of claim 8 , wherein an integrated circuit includes the power management circuitry.

10. Power management circuitry, comprising:

communication circuitry configured to receive power supply information from a plurality of powered devices and a plurality of power supply devices, wherein the power supply information includes information associated with electrical power supplied from the plurality of power supply devices and power requirements of the plurality of powered devices; and

power regulator circuitry configured to:

determine a regulated power signal associated with the supplied electrical power according to the power supply information and a weighted averaged load between the plurality of powered devices based on priority information of the plurality of powered devices; and

arbitrate the regulated power signal between the plurality of powered devices according to the power supply information.

11. The power management circuitry of claim 10 , wherein the power regulator circuitry is configured to arbitrate the regulated power signal according to respective power supply needs of the plurality of powered devices.

12. The power management circuitry of claim 11 , wherein the respective power supply needs of the plurality of powered devices includes respective loads of the plurality of powered devices.

13. The power management circuitry of claim 10 , wherein the power regulator circuitry is configured to arbitrate the regulated power signal according to respective priorities of access to supplied power for the plurality of powered devices.

14. The power management circuitry of claim 10 , wherein the power regulator circuitry is configured to determine the regulated power signal according to the power supply information associated with a powered device of the plurality of the powered devices having a highest priority of access to supplied power.

15. The power regulator circuitry of claim 1 , wherein communication interface circuitry includes wireless communication circuitry and the wireless communication circuitry is configured to receive the power supply information over a wireless network.

16. The method of claim 8 , wherein the receiving of the power supply information is over a wireless network.

17. The power management circuitry of claim 10 , wherein the communication circuitry includes wireless communication circuitry and the wireless communication circuitry is configured to receive the power supply information over a wireless network.

18. The power regulator circuitry of claim 1 , wherein the power regulator circuitry is internal to an integrated circuit and the plurality of power sources are external to the integrated circuit.

19. The method of claim 9 , wherein the plurality of power supply devices are external to the integrated circuit.

20. The power management circuitry of claim 10 , wherein the power management circuitry is internal to an integrated circuit and the plurality of power supply devices are external to the integrated circuit.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 9,385,856 TO 9,385,756 PREVIOUSLY RECORDED AT REEL: 47349 FRAME: 001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 051144/0648 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047229 FRAME 0408. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047349/0001 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047229/0408 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 20, 2014
From: KIM, NEIL Y.; VORENKAMP, PIETER
To: BROADCOM CORPORATION
Reel/Frame 033979/0899 →