Area efficient traffic generator
A packet generation and inspection system for monitoring the performance of one or more flows on a packet network comprises a processor and memory coupled to each other and to a network bus. The memory stores instructions to be executed by the processor and data to be modified by the execution of the instructions. A processor-controlled arbiter is coupled with the processor and the network bus, and upon reception of a packet on the bus or prior to transmission of a packet on the bus for one of said flows, the arbiter requests execution by the processor of selected instructions stored in the memory by providing the processor with the address of the selected instructions in the memory. The memory provides the processor with data associated with the selected instructions, and the processor modifies the data upon execution of the selected instructions.
1. A packet generation and inspection system to monitor the performance of one or more flows on a packet network, said system comprising:
a processor and memory coupled to each other and to a bus of the packet network, said memory storing operating codes corresponding to commands to be executed by said processor in association with data to be modified by the execution of said commands, said commands and data comprising information to build and manage packet generation of said one or more flows, wherein said commands corresponding to said operating codes are pre-programmed in said processor;
a processor-controlled arbiter coupled with said processor and said bus, said arbiter controlling access to said memory, said arbiter requesting execution, upon reception of a packet on the bus or prior to transmission of a packet on the bus for one of said flows, by said processor of selected operating codes stored in said memory by providing said processor with the address of said selected operating codes in said memory, and
wherein said memory provides said processor with data associated with the selected operating codes, and said processor modifies said data upon execution of commands corresponding to the selected operating codes.
2. The packet generation and inspection system of claim 1 which includes a traffic generator and a traffic inspector coupled to said processor and said arbiter.
3. The packet generation and inspection system of claim 2 in which said traffic generator creates and sends test packets to said arbiter, and said traffic inspector receives and analyzes test packets to gather performance statistics and sends said statistics to said arbiter.
4. The packet generation and inspection system of claim 1 in which processor is implemented as a field programmable gate array (FPGA).
5. The packet generation and inspection system of claim 1 in which the addresses of the operating codes stored in said memory are offsets that partition the memory in different segments that can be used to execute different functions.
6. A method of generating and inspecting packets to monitor the performance of one or more flows on a packet network, said method comprising
storing in association in a memory operating codes corresponding to commands to be executed by a processor and data to be modified by the execution of said commands, said commands and data comprising information to build and manage packet generation of said one or more flows, said memory and said processor being coupled to each other and to a bus of the packet network and wherein said commands corresponding to said operating codes are pre-programmed in said processor,
upon reception of a packet on the bus or prior to transmission of a packet on the bus for one of said flows, an arbiter controlling access to said memory, said arbiter requesting execution by said processor of selected operating codes stored in said memory by providing said processor with the address of said selected operating codes in said memory, and
providing said processor with data associated with the selected operating codes and modifying said data in said processor upon execution of commands corresponding to the selected operating codes.
7. The method of claim 6 which includes creating and sending test packets to said bus, receiving test packets from said bus, analyzing received test packets to gather performance statistics, and sending said statistics to said processor.
8. The method of claim 6 in which processor is implemented as a field programmable gate array (FPGA).
9. The method of claim 6 in which the addresses of the operating codes stored in said memory are offsets that partition the memory in different segments that can be used to execute different functions.