Method of manufacturing a capacitor
A method of forming a device comprises forming a through via extending from a surface of a substrate into the substrate. The method also comprises forming a first insulating layer over the surface of the substrate. The method further comprises forming a first metallization layer in the first insulating layer, the first metallization layer electrically connecting the through via. The method additionally comprises forming a capacitor over the first metallization layer. The capacitor comprises a first capacitor dielectric layer over the first metallization layer and a second capacitor dielectric layer over the first capacitor dielectric layer. The method also comprises forming a second metallization layer over and electrically connecting the capacitor.
1. A method of forming a device, the method comprising:
forming a through via within an interposer, the through via extending through at least a portion of the interposer;
forming a first metallization layer over the interposer and electrically connected with the through via;
forming a first insulating layer over the first metallization layer;
forming a second metallization layer over the first insulating layer, the second metallization layer being partially within the first insulating layer and electrically connected with the first metallization layer;
forming a second insulating layer over the second metallization layer, the second metallization layer being partially within the second insulating layer;
forming a capacitor in the first insulating layer, the capacitor being positioned between the first metallization layer and the second metallization layer;
forming a first via plug in the first insulating layer, the capacitor being electrically connected with the second metallization layer through the first via plug; and
forming a second via plug in the first insulating layer, the first metallization layer being electrically connected with the second metallization layer through the second via plug.
2. The method of claim 1 , wherein the interposer comprises silicon.
3. The method of claim 1 , wherein the through via comprises copper.
4. The method of claim 1 , wherein the capacitor comprises a stack of at least two metal-insulator-metal (MIM) capacitors.
5. The method of claim 1 , wherein the capacitor comprises dual capacitor dielectric layers.
6. The method of claim 1 , further comprising one or more dielectric layers between a bottom electrode of the capacitor and the first metallization layer.
7. The method of claim 1 , wherein the capacitor comprises a planar capacitor.
8. The method of claim 1 , wherein the capacitor comprises a first electrode layer, a second electrode layer, a third electrode layer, a first capacitor dielectric layer between the first electrode layer and the second electrode layer, and a second capacitor dielectric layer between the second electrode layer and the third electrode layer.
9. The method of claim 8 , further comprising:
wherein the first via plug electrically connects to at least one of the first electrode layer, the second electrode layer and the third electrode layer.
10. A method of forming a device, the method comprising:
forming a through via in a substrate, the through via extending through the substrate;
forming a first metallization layer over the substrate, the first metallization layer being electrically connected with the through via;
forming a first insulating layer over the first metallization layer;
forming a second metallization layer over the first insulating layer, the second metallization layer being partially within the first insulating layer and electrically connected with the first metallization layer;
forming an etch stop layer over the first insulating layer;
forming a second insulating layer over the etch stop layer, the second metallization layer being partially within the first insulating layer between a lower surface of the etch stop layer and the first metallization layer, and partially within the second insulating layer;
forming a capacitor in the first insulating layer, the capacitor being positioned between the first metallization layer and the second metallization layer, wherein the capacitor comprises a first electrode layer, a second electrode layer, a third electrode layer, a first capacitor dielectric layer between the first electrode layer and the second electrode layer, and a second capacitor dielectric layer between the second electrode layer and the third electrode layer;
forming a first via plug in the first insulating layer, the capacitor being electrically connected with the second metallization layer through the first via plug; and
forming a second via plug in the first insulating layer, the first metallization layer being electrically connected with the second metallization layer through the second via plug.
11. The method of claim 10 , wherein the substrate is a silicon interposer.