SEMICONDUCTOR MEMORY DEVICE

1 . A semiconductor memory device comprising:

a nonvolatile device array including write-once nonvolatile devices arranged in rows and columns;

one or more row select lines corresponding to rows of the nonvolatile device array;

a row control circuit connected to one ends of the row select lines;

one or more column select lines corresponding to columns of the nonvolatile device array;

a column control circuit connected to one ends of the column select lines;

a flip-flop circuit provided at least on a side of the nonvolatile device array opposite to the row control circuit or on a side of the nonvolatile device array opposite to the column control circuit; and

an inactivation unit configured to inactivate the row select lines or the column select lines based on a first control signal.

2 . The semiconductor memory device of claim 1 , wherein

the inactivation unit include a predecode signal generation circuit configured to inactivate a predecode signal to inactivate a corresponding one of the row select lines or a corresponding one of the column select lines, the predecode signal logically transitioning based on the first control signal.

3 . The semiconductor memory device of claim 2 , wherein

the predecode signal generation circuit inactivates the predecode signal based on the first control signal and a second control signal for selecting the nonvolatile device array.

4 . The semiconductor memory device of claim 2 , wherein

the predecode signal generation circuit inactivates the predecode signal based on a first synchronous signal and the first control signal.

5 . The semiconductor memory device of claim 1 , further comprising:

an open unit configured to open the column select lines, excluding one of the column select lines, when the column select lines are not inactivated, or the row select lines, excluding one of the row select lines, when the row select lines are not inactivated.

6 . The semiconductor memory device of claim 5 , wherein

the open unit includes n-type MIS transistors each having a drain connected to a corresponding one of the row select lines and a gate receiving a signal obtained by logically combining a first synchronous signal and a third control signal.

7 . The semiconductor memory device of claim 6 ,

the open unit changes gate potentials of the n-type MIS transistors to a low level to open the row select lines, excluding an active one of the row select lines.

8 . The semiconductor memory device of claim 5 , wherein

the open unit includes n-type MIS transistors each having a drain connected to a corresponding one of the column select lines and a gate receiving a signal obtained by logically combining a first synchronous signal and a third control signal.

9 . The semiconductor memory device of claim 8 , wherein

the open unit changes gate potentials of the n-type MIS transistors to a low level to open the column select lines, excluding an active one of the column select lines.

10 . The semiconductor memory device of claim 1 , wherein

the flip-flop circuit latches electric potentials of the row select lines or the column select lines based on a fourth control signal.

11 . The semiconductor memory device of claim 1 , wherein

the flip-flop circuit includes flip-flop circuits provided on a side of the nonvolatile device array opposite to the row control circuit and on a side of the nonvolatile device array opposite to the column control circuit.

12 . The semiconductor memory device of claim 1 , wherein

the nonvolatile device is an electric fuse made of a gate material of a transistor.