Transmit/receive channel for ultrasound applications

1. A device, comprising:

a first voltage reference node;

a second voltage reference node;

an output node;

a clamp node;

a first high-voltage switching transistor having a first conduction terminal coupled to the first voltage reference node and a second conduction terminal coupled to the clamp node;

a second high-voltage switching transistor having a first conduction terminal coupled to the clamp node and a second conduction terminal coupled to the second voltage reference node;

a third high-voltage switching transistor having a first conduction terminal coupled to the first voltage reference node, a control terminal coupled to the clamp node, and a second conduction terminal coupled to the output node; and

a voltage regulator coupled between the output node and the clamp node.

2. The device of claim 1 wherein the second and third high-voltage switching transistors have substantially identical operating characteristics.

3. The device of claim 1 wherein the voltage regulator comprises a Zener diode.

4. The device of claim 3 wherein a cathode terminal of the Zener diode is coupled to a drain terminal of the second high-voltage switching transistor and an anode terminal of the Zener diode is coupled to a source terminal of the third high-voltage switching transistor.

5. The device of claim 1 wherein the voltage regulator comprises:

a first plurality of diodes coupled together in series between the output node and the clamp node; and

a diode coupled in antiseries across the first plurality of diodes.

6. The device of claim 1 wherein, in operation, the output node provides an ultrasound transducer drive signal.

7. The device of claim 1 , comprising:

a first input driver coupled to a control terminal of the first high-voltage switching transistor; and

a second input driver coupled to a control terminal of the second high-voltage switching transistor.

8. The device of claim 1 wherein the first high-voltage switching transistor is a PMOS transistor, the second high-voltage switching transistor is an NMOS and the third high-voltage switching transistor is an NMOS.

9. A system, comprising:

a high-voltage shifter having:

a first voltage reference node;

a second voltage reference node;

an output node;

a clamp node;

a first high-voltage switching transistor having a first conduction terminal coupled to the first voltage reference node and a second conduction terminal coupled to the clamp node;

a second high-voltage switching transistor having a first conduction terminal coupled to the clamp node and a second conduction terminal coupled to the second voltage reference node;

a third high-voltage switching transistor having a first conduction terminal coupled to the first voltage reference node, a control terminal coupled to the clamp node, and a second conduction terminal coupled to the output node; and

a voltage regulator coupled between the output node and the clamp node; and

a voltage clamp coupled to the clamp node and to a third voltage reference node.

10. The system of claim 9 wherein the voltage clamp comprises:

a first clamp switching transistor having a first conduction terminal coupled to the third voltage reference node;

a first diode coupled to the clamp node and to a second conduction terminal of the first clamp switching transistor;

a second clamp switching transistor having a first conduction terminal coupled to the third reference voltage node; and

a second diode coupled to the clamp node and to a second conduction terminal of the second clamp switching transistor.

11. The system of claim 10 wherein,

the first high-voltage switching transistor and the first clamp switching transistor are transistors having substantially identical operational characteristics; and

the second high-voltage switching transistor, the third high-voltage switching transistor and the second clamp transistor are transistors having substantially identical operational characteristics.

12. The system of claim 11 wherein the first clamp transistor is a PMOS transistor and the second clamp transistor is an NMOS transistor.

13. The system of claim 10 , comprising:

a first input driver coupled to a control terminal of the first high-voltage switching transistor;

a second input driver coupled to a control terminal of the second high-voltage switching transistor;

a third input driver coupled to a control terminal of the first clamp switching transistor; and

a fourth input driver coupled to a control terminal of the second clamp switching transistor.

14. The system of claim 13 , comprising a controller, which, in operation, generates control signals to control the input drivers.

15. The system of claim 9 , comprising:

an ultrasound transducer coupled to the output node.

16. The system of claim 9 wherein the voltage regulator comprises a Zener diode.

17. The system of claim 9 wherein the voltage regulator comprises:

a first plurality of diodes coupled together in series between the output node and the clamp node; and

a diode coupled in antiseries across the first plurality of diodes.

18. A method, comprising:

in a first mode of operation of an ultrasound system,

conducting a bias current through a first switching transistor and a voltage regulator of a voltage shifter;

conducting a driving current through a second switching transistor of the voltage shifter; and

conducting a sum of the bias current and the driving current through an ultrasound transducer;

in a second mode of operation of the ultrasound system,

conducting the driving current through the ultrasound transducer, the voltage regulator and a third switching transistor of the voltage shifter;

in a third mode of operation of the ultrasound system,

conducting the bias current through a first clamp transistor and the voltage regulator;

conducting the driving current through second switching transistor of the voltage shifter; and

conducting the sum of the bias current and the driving current through the ultrasound transducer; and

in a fourth mode of operation of the ultrasound system,

conducting the driving current through the ultrasound transducer and a second clamp transistor.

19. The method of claim 18 wherein the first switching transistor of the voltage shifter and the first clamp transistor are PMOS transistors having substantially identical operational characteristics.

20. The method of claim 19 wherein the second switching transistor of the voltage shifter, the third switching transistor of the voltage shifter and the second clamp transistor are NMOS transistors having substantially identical operational characteristics.

21. The method of claim 18 wherein the voltage regulator comprises a Zener diode.