IP Library Granted Patent US 9,405,356
Granted Patent B1
US 9,405,356 · App. 14/519,396 · Granted Aug 2, 2016

Temperature compensation in data storage device

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Quick Facts
Patent No.
US 9,405,356
App. No.
14/519,396
Granted
Aug 2, 2016
Kind
B1
Abstract

Systems and methods are disclosed managing power and/or temperature in a data storage system. A hybrid data storage device comprises a disk component and a non-volatile semiconductor memory component. The data storage device further comprises a temperature sensor and a controller configured to receive a temperature signal from the temperature sensor indicating a temperature of at least a portion of the data storage device and, when the temperature is determined to be greater than a first temperature, manage power to the semiconductor memory according to a first power throttling state.

Claims (51)

1. A data storage device comprising:

a disk;

a non-volatile semiconductor memory;

a temperature sensor; and

a controller configured to:

receive a temperature signal from the temperature sensor indicating a temperature of at least a portion of the data storage device; and

when the temperature is determined to be greater than a first temperature, manage power to the semiconductor memory according to a first power throttling state;

wherein the first power throttling state is designed to allow the data storage device to maintain device temperature below a critical level when executing a workload requiring at least partially simultaneous access to both the disk and the semiconductor memory.

2. The data storage device of claim 1 , wherein said managing power to the semiconductor memory comprises setting one or more timer values to reduced value(s).

3. The data storage device of claim 1 , wherein the controller is further configured to manage power to the semiconductor memory according to a second power throttling state when the temperature is less than the first temperature but greater than a second temperature that is lower than the first temperature.

4. A data storage device comprising:

a disk;

a non-volatile semiconductor memory;

a temperature sensor;

a controller; and

a bridge device communicatively coupled to the semiconductor memory and the controller:

wherein the controller is configured to:

receive a temperature signal from the temperature sensor indicating a temperature of at least a portion of the data storage device;

when the temperature is determined to be greater than a temperature threshold, set first and second timer values according to a power throttling state;

power down the bridge device based on the first timer value; and

power down the semiconductor memory based on the second timer value.

5. A data storage device comprising:

a disk;

a non-volatile semiconductor memory;

a temperature sensor; and

a controller configured to:

receive a temperature signal from the temperature sensor indicating a temperature of at least a portion of the data storage device; and

when the temperature is determined to be greater than a first temperature, manage power in the data storage device at least in part by setting first and second timer values to first and second reduced timer values, respectively, according to a first power throttling state.

6. The data storage device of claim 5 , wherein the first reduced timer value is approximately 100 ms and the second reduced timer value is approximately 20 ms.

7. The data storage device of claim 5 , wherein the controller is further configured to set the first and second timer values to third and fourth reduced timer values, respectively, according to a second power throttling state when the temperature is less than the first temperature but greater than a second temperature lower than the first temperature.

8. The data storage device of claim 7 , wherein the third reduced timer value is approximately 280 ms and the fourth reduced timer value is approximately 20 ms.

9. The data storage device of claim 3 , wherein the first temperature is greater than 50° C.

10. The data storage device of claim 9 , wherein the second temperature is greater than 35° C.

11. A data storage device comprising:

a disk;

a temperature sensor;

a non-volatile semiconductor memory; and

a controller configured to:

determine that a number of commands received by the controller from a host device within a predetermined period of time exceeds a threshold number of commands;

in response to said determination, determine whether a temperature of at least a portion of the data storage device is greater than a first temperature threshold based at least in part on a temperature signal received from the temperature sensor; and

when the temperature is determined to be greater than the temperature threshold, manage power to the semiconductor memory according to a power throttling state;

wherein the power throttling state is designed to allow the data storage device to maintain device temperature below a critical level when executing a workload requiring at least partially simultaneous access to both the disk and the semiconductor memory.

12. A method of managing temperature in a data storage device, the method comprising:

by a controller of the data storage device comprising a disk and a non-volatile semiconductor memory:

receiving a temperature signal from a temperature sensor indicating a temperature of at least a portion of the data storage device;

when the temperature is determined to be greater than a first temperature, managing power to the semiconductor memory by setting first and second timer values according to a first power throttling state;

powering down a bridge device communicatively coupled to both the semiconductor memory and the controller based on the first timer value; and

powering down the semiconductor memory based on the second timer value.

13. The method of claim 12 , further comprising setting the first and second timer values according to a second power throttling state when the temperature is less than the first temperature but greater than a second temperature that is lower than the first temperature.

14. The method of claim 13 , wherein setting the first and second timer values according to the first power throttling state comprises setting the first and second timer values to first and second reduced timer values, respectively.

15. The method of claim 14 , wherein setting the first and second timer values according to the second power throttling state comprises setting the first and second timer values to third and fourth reduced timer values, respectively.

Assignments (7)
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 038744 FRAME 0481 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0556 →
RELEASE OF SECURITY INTEREST Recorded Mar 5, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 045501/0714 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038722/0229 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038744/0281 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038744/0481 →