Dividing a single phase pulse-width modulation signal into a plurality of phases

1. A method of dividing a single phase pulse-width modulation (PWM) signal into a plurality of phases, the method comprising:

receiving, from a phase controller by a PWM frequency divider, an input pulse train comprising a period; and

dividing, by the PWM frequency divider, the input pulse train amongst a plurality of output phases of the PWM frequency divider, including, at the onset of each period of the input pulse train:

providing, on a next output phase of the PWM frequency divider, an output pulse train that transitions from a tri-state voltage level to a logic high voltage level at the onset of a period of the input pulse train and transitions from the logic high voltage level to a logic low voltage level toward the end of the period of the input pulse train; and

holding all other output phases at the tri-state voltage level that is between the logic high voltage level and the logic low voltage level.

2. The method of claim 1 wherein the PWM frequency divider is coupled to a Direct Current (DC)-DC converter via the plurality of output phases, the DC-DC converter comprising:

a directly coupled inductor comprising a coil element coupled to an output filter and a load; and

a plurality of power-switching phases, with each phase comprising a high-side switch, a low-side switch and a driver, wherein the high-side switch of each power-switching phase is configured, when activated via the driver, to couple a voltage source to the coil element and the low-side switch of each power-switching phase is configured, when activated via the driver, to couple the coil element to a ground voltage, wherein the driver is coupled to one of the plurality of output phases of the PWM frequency divider and the driver is configured to activate the high side switch and deactivate the low side switch when the output pulse train of the output phase is a logic high voltage level, the driver is configured to activate the low side switch and deactivate the high side switch when the output pulse train of the output phase is a logic low voltage level, and the driver is configured to deactivate the high and low side switches when the output pulse train of the output phase is a tri-state voltage level; and

the method further comprises:

responsive to receiving the output pulse train of the plurality of output phases of the frequency divider:

alternately activating, by the drivers of the plurality of power-switching phases, each switch, wherein no two switches are activated at the same time.

3. The method of claim 2 wherein alternatively activating each switch further comprises:

activating each high-side switch for a period of time according to:

D

N

where D represents a duty cycle and N represents the number of power-switching phases; and

activating each low-side switch for a period of time according to:

(

1

-

D

)

N

.

4. The method of claim 2 wherein the number of power-switching phases is inversely proportional to the duty cycle of activating the switches and thereby inversely proportional to the inductance of the directly coupled inductor.

5. The method of claim 2 wherein current ripple experienced by the filter and the load comprises:

1

f

*

L

OL

*

(

1

-

V

OUT

V

IN

)

*

V

OUT

N

,

where f represents the frequency of alternatively activating each switch, L OL represents the open loop inductance of the directly coupled inductor, N represents the number of power-switching phases, V IN represents the voltage of the voltage source and V OUT represents the voltage experienced at the filter and load.

6. The method of claim 2 wherein each high-side switch and each low-side switch comprises a Field Effect Transistor.

7. The method of claim 1 wherein the PWM frequency divider comprises a Field Programmable Gate Array (FPGA).

8. An apparatus for dividing a single phase pulse-width modulation (PWM) signal into a plurality of phases, the apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of:

receiving, from a phase controller by a PWM frequency divider, an input pulse train comprising a period; and

dividing, by the PWM frequency divider, the input pulse train amongst a plurality of output phases of the PWM frequency divider, including, at the onset of each period of the input pulse train:

providing, on a next output phase of the PWM frequency divider, an output pulse train that transitions from a tri-state voltage level to a logic high voltage level at the onset of a period of the input pulse train and transitions from the logic high voltage level to a logic low voltage level toward the end of the period of the input pulse train; and

holding all other output phases at the tri-state voltage level that is between the logic high voltage level and the logic low voltage level.

9. The apparatus of claim 8 wherein the PWM frequency divider is coupled to a Direct Current (DC)-DC converter via the plurality of output phases, the DC-DC converter comprising:

a directly coupled inductor comprising a coil element coupled to an output filter and a load; and

a plurality of power-switching phases, with each phase comprising a high-side switch, a low-side switch and a driver, wherein the high-side switch of each power-switching phase is configured, when activated via the driver, to couple a voltage source to the coil element and the low-side switch of each power-switching phase is configured, when activated via the driver, to couple the coil element to a ground voltage, wherein the driver is coupled to one of the plurality of output phases of the PWM frequency divider and the driver is configured to activate the high side switch and deactivate the low side switch when the output pulse train of the output phase is a logic high voltage level, the driver is configured to activate the low side switch and deactivate the high side switch when the output pulse train of the output phase is a logic low voltage level, and the driver is configured to deactivate the high and low side switches when the output pulse train of the output phase is a tri-state voltage level; and

the apparatus further comprises computer program instructions that when executed causes the apparatus to carry out the steps of:

responsive to receiving the output pulse train of the plurality of output phases of the frequency divider:

alternately activating, by the drivers of the plurality of power-switching phases, each switch, wherein no two switches are activated at the same time.

10. The apparatus of claim 9 wherein alternatively activating each switch further comprises:

activating each high-side switch for a period of time according to:

D

N

where D represents a duty cycle and N represents the number of power-switching phases; and

activating each low-side switch for a period of time according to:

(

1

-

D

)

N

.

11. The apparatus of claim 9 wherein the number of power-switching phases is inversely proportional to the duty cycle of activating the switches and thereby inversely proportional to the inductance of the directly coupled inductor.

12. The apparatus of claim 9 wherein current ripple experienced by the filter and the load comprises:

1

f

*

L

OL

*

(

1

-

V

OUT

V

IN

)

*

V

OUT

N

,

where f represents the frequency of alternatively activating each switch, L OL represents the open loop inductance of the directly coupled inductor, N represents the number of power-switching phases, V IN represents the voltage of the voltage source and V OUT represents the voltage experienced at the filter and load.

13. The apparatus of claim 9 wherein each high-side switch and each low-side switch comprises a Field Effect Transistor.

14. The apparatus of claim 8 wherein the PWM frequency divider comprises a Field Programmable Gate Array (FPGA).