IP Library Granted Patent US 9,312,878
Granted Patent B1
US 9,312,878 · App. 14/522,842 · Granted Apr 12, 2016

Superconductor analog to digital converter

Inventors: Amol Inamdar (Elmsford, NY); Deepnarayan Gupta (Briarcliff Manor, NY)
Assignee: Hypres, Inc.
H03M3/02H03M1/0854H03M1/12H03M1/68
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,312,878
App. No.
14/522,842
Granted
Apr 12, 2016
Kind
B1
Abstract

Superconductor analog-to-digital converters (ADC) offer high sensitivity and large dynamic range. One approach to increasing the dynamic range further is with a subranging architecture, whereby the output of a coarse ADC is converted back to analog and subtracted from the input signal, and the residue signal fed to a fine ADC for generation of additional significant bits. This also requires a high-gain broadband linear amplifier, which is not generally available within superconductor technology. In a preferred embodiment, a distributed digital fluxon amplifier is presented, which also integrates the functions of integration, filtering, and flux subtraction. A subranging ADC design provides two ADCs connected with the fluxon amplifier and subtractor circuitry that would provide a dynamic range extension by about 30-35 dB.

Claims (38)

1. A signal processing system, comprising:

an input configured to receive an analog signal;

a first electronic circuit configured to selectively produce a stream of quantized pulses which represent an amplitude of the received analog signal delayed with respect to the analog signal;

a time delay structure configured to control a time delay of the received analog signal with respect to the stream of quantized pulses, and producing a delayed received analog signal;

a second electronic circuit configured to selectively produce an analog residue signal representing a difference between an amplitude of the delayed received analog signal and the represented amplitude of the received analog signal;

a third electronic circuit configured to selectively produce a quantized representation of the analog residue signal; and

a digital signal processor, configured to receive the stream of quantized pulses and the quantized representation of the analog residue signal, and to generate a signal representing the amplitude of the received analog signal with an accuracy greater than the stream of quantized pulses.

2. The signal processing system of claim 1 , wherein at least one of the stream of quantized pulses and the quantized representation of the analog residue signal are quantized in units of magnetic flux.

3. The signal processing system of claim 2 , wherein the first electronic circuit comprises a delta modulator, and the third electronic circuit comprises a sigma-delta modulator.

4. The signal processing system of claim 1 , wherein at least one of the first electronic circuit and the third electronic circuit comprises a phase-modulation-demodulation modulator.

5. The signal processing system of claim 1 , wherein the second electronic circuit comprises at least two magnetically coupled conductive elements.

6. The signal processing system of claim 1 , further comprising an amplifier to amplify the stream of quantized pulses, and at least one integration element configured to smooth the amplified stream of quantized pulses, before passing the smoothed amplified stream of quantized pulses to the second electronic circuit.

7. The signal processing system of claim 6 , wherein the amplifier comprises at least one Josephson junction, and the amplified stream of quantized pulses has a plurality of pulses corresponding to each pulse of the stream of quantized pulses.

8. The signal processing system of claim 1 , wherein the signal representing the amplitude of the received analog signal with an accuracy greater than the stream of quantized pulses comprises a phase-modulated digital signal.

9. The signal processing system of claim 1 , further comprising an amplifier to amplify the stream of quantized pulses, wherein the amplified stream of quantized pulses comprises at least two parallel streams of digital pulses representing signal components of unequal logical weight.

10. The signal processing system of claim 1 , further comprising a digital filter having at least one information storage element, configured to receive the stream of quantized pulses over time and to selectively produce a digitally filtered output dependent on the stream of quantized pulses and time.

11. The signal processing system of claim 10 , wherein the digital filter comprises a decimator that reduces an output sampling rate.

12. The signal processing system of claim 1 , wherein the time delay structure comprises a digitally adjustable time delay structure.

13. The signal processing system of claim 1 , wherein the first electronic circuit has at least two quantization thresholds.

14. A method of signal processing, comprising:

receiving an analog signal;

selectively producing a stream of quantized pulses which represent an amplitude of the received analog signal delayed with respect to the analog signal with a first electronic circuit;

controlling a time delay of the received analog signal with respect to the stream of quantized pulses, and producing a delayed received analog signal;

selectively producing an analog residue signal representing a difference between an amplitude of the delayed received analog signal and the represented amplitude of the received analog signal with a second electronic circuit;

selectively producing a quantized representation of the analog residue signal with a third electronic circuit; and

receiving the stream of quantized pulses and the quantized representation of the analog residue signal with a digital signal processor, and generating a signal representing the amplitude of the received analog signal with an accuracy greater than the stream of quantized pulses.

15. The method of claim 14 , further comprising amplifying the stream of quantized pulses, integrating the amplified stream of quantized pulses, and feeding the integrated amplified stream of quantized pulses to a magnetic flux subtractor.

16. The method of claim 15 , wherein the amplified stream of quantized pulses comprises a plurality of pulses corresponding to each pulse of the stream of quantized pulses.

17. The method of claim 14 , wherein the stream of quantized pulses has an associated clock having a clock frequency in excess of 40 GHz.

18. The method of claim 14 , wherein the digital signal processor generates the digital in dependence on at least a past history of at least one quantized signal.

19. The method of claim 14 , wherein the time delay is digitally controlled.

20. A method of signal processing, comprising:

receiving an analog signal;

selectively producing a stream of quantized pulses which represent a waveform of the received analog signal controllably delayed in time with respect to the analog signal;

controlling a time delay of the received analog signal with respect to the stream of quantized pulses, and producing a delayed received analog signal;

selectively producing an analog residue signal representing a quantitative difference between a waveform of the delayed received analog signal and the represented waveform of the received analog signal;

selectively producing a quantized representation of the analog residue signal; and

receiving the stream of quantized pulses and the quantized representation of the analog residue signal with a digital signal processor, and generating a signal representing the waveform of the received analog signal with an accuracy greater than the stream of quantized pulses.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Aug 6, 2024
From: AVIDBANK
To: HYPRES, INC.
Reel/Frame 068348/0909 →
SECURITY INTEREST Recorded Jun 17, 2021
From: HYPRES, INC.
To: AVIDBANK
Reel/Frame 056617/0116 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 24, 2014
From: INAMDAR, AMOL; GUPTA, DEEPNARAYAN
To: HYPRES, INC.
Reel/Frame 034027/0017 →
Continuity (3)
Continuation 13482266 · May 29, 2012
Continuation 12542585 · Aug 17, 2009
Provisional Application 61089489 · Aug 15, 2008