Self-addressing memory
View Patent ↗Techniques are disclosed relating to self-addressing memory. In one embodiment, an apparatus includes a memory and addressing circuitry coupled to or comprised in the memory. In this embodiment, the addressing circuitry is configured to receive memory access requests corresponding to a specified sequence of memory accesses. In this embodiment, the memory access requests do not include address information. In this embodiment, the addressing circuitry is further configured to assign addresses to the memory access requests for the specified sequence of memory accesses. In some embodiments, the apparatus is configured to perform the memory access requests using the assigned addresses.
1. A method, comprising:
receiving, by addressing circuity, memory access requests corresponding to a specified sequence of memory accesses from a program, wherein the memory access requests do not include address information;
assigning, by the addressing circuitry, addresses to the memory access requests for the specified sequence of memory accesses, wherein the addresses are assigned according to the specified sequence, wherein ordering and addresses of the specified sequence are determined during compilation of the program, wherein the compilation includes execution of portions of the program to determine the sequence of memory accesses; and
performing, by a memory, the sequence of memory accesses using the assigned addresses.
2. The method of claim 1 , further comprising:
storing addresses for the specified sequence of memory accesses, wherein the stored addresses are generated during compilation of a program.
3. The method of claim 1 , further comprising:
configuring the addressing circuitry using information specifying addresses for a second sequence of memory accesses.
4. The method of claim 1 , further comprising:
maintaining, by the addressing circuitry, a read counter for read accesses to the memory and a write counter for write accesses to the memory;
wherein the assigning is based on the read counter and the write counter.
5. The method of claim 1 , further comprising:
assigning, by the addressing circuitry, addresses to the memory access requests for multiple specified sequences of memory accesses corresponding to different programs.
6. The method of claim 1 , wherein the specified sequence of memory accesses is based on a parity check matrix for a low-density parity-check (LDPC) decoder.
7. A method, comprising:
determining, by a computing system, a sequence of memory accesses for a program by compiling an input program that comprises the sequence of memory accesses to determine the order of the sequence of memory accesses and addresses of the sequence of memory accesses, wherein the compiling includes executing portions of the input program to determine the sequence of memory accesses;
generating, by the computing system, information specifying addresses for the sequence of memory accesses; and
configuring, by the computing system, addressing circuitry using the information, wherein the addressing circuitry is included in or coupled to a memory, wherein after said configuring the addressing circuitry is operable to assign addresses to memory access requests corresponding to the sequence of memory accesses, wherein the memory access requests do not include address information.
8. The method of claim 7 , wherein the configuring is performed using one or more programmable hardware elements.
9. The method of claim 7 , wherein the configuring is performed by transferring the information to a table.
10. The method of claim 7 , wherein the determining is based on a parity check matrix for a low-density parity-check (LDPC) decoder.
11. The method of claim 7 , wherein the sequence of memory accesses includes non-sequential addresses.
12. An apparatus, comprising:
a memory; and
addressing circuitry coupled to or comprised in the memory, wherein the addressing circuitry is configured to:
receive memory access requests corresponding to a specified sequence of memory accesses from a program, wherein the memory access requests do not include address information; and
assign addresses to the memory access requests for the specified sequence of memory accesses, wherein the addresses are assigned according to the specified sequence, wherein the specified sequence is determined during compilation of the program, wherein the compilation includes execution of portions of the program to determine the sequence of memory accesses.
13. The apparatus of claim 12 , wherein the addressing circuitry is further configured to:
store addresses for the specified sequence of memory accesses.
14. The apparatus of claim 12 , wherein the addressing circuitry is programmable to assign addresses to memory access requests for a second specified sequence of memory accesses.
15. The apparatus of claim 12 , wherein the addressing circuitry is further configured to:
maintain a read counter for read accesses to the memory and a write counter for write accesses to the memory; and
assign the addresses based on the read counter and the write counter.
16. The apparatus of claim 12 , wherein the addressing circuitry is configured with addresses for sequences of memory access requests corresponding to multiple different programs.
17. The apparatus of claim 12 , wherein the specified sequence of memory accesses includes non-sequential addresses and is based on a parity check matrix for a low-density parity-check (LDPC) decoder.
18. The apparatus of claim 12 , wherein the memory is multi-ported and is configured to initiate a plurality of memory accesses in a given cycle.
19. The apparatus of claim 12 , further comprising circuitry configured to perform one or more of: caching, pre-fetching, or data forwarding based on upcoming memory access addresses in the sequence of memory accesses.