IP Library Granted Patent US 9,690,928
Granted Patent B2
US 9,690,928 · App. 14/523,886 · Granted Jun 27, 2017

Computing platform security methods and apparatus

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,690,928
App. No.
14/523,886
Granted
Jun 27, 2017
Kind
B2
Abstract

Computing platform security methods and apparatus are disclosed. An example apparatus includes a security application to configure a security task, the security task to detect a malicious element on a computing platform, the computing platform including a central processing unit and a graphics processing unit; and an offloader to determine whether the central processing unit or the graphics processing unit is to execute the security task; and when the graphics processing unit is to execute the security task, offload the security task to the graphics processing unit for execution.

Claims (33)

1. A method, comprising:

selecting, by executing an instruction with a processor, a plurality of processes to be monitored via a sliding window;

shifting, by executing an instruction with the processor, the sliding window through a progression of the plurality of processes;

mapping, by executing an instruction with the processor, memory corresponding to the plurality of processes within the sliding window to a virtual address space; and

executing a scan of the mapped memory.

2. A method as defined in claim 1 , further including defining a condition to determine an aspect of a first one of the plurality of processes to be mapped to the virtual address space.

3. A method as defined in claim 1 , further including selecting a window size to define the sliding window.

4. A method as defined in claim 1 , wherein the executing of the scan of the mapped memory is performed by a graphics processing unit.

5. A method as defined in claim 4 , further including verifying a match found by the scan of the mapped memory.

6. A method as defined in claim 1 , wherein the shifting of the sliding window through the progression of the plurality of processes including shifting the sliding window after the memory of a current iteration is mapped to the virtual address space.

7. A method as defined in claim 1 , wherein the virtual address space corresponds to a user-mode client of a computing platform.

8. An apparatus, comprising:

a process selector to select a plurality of processes to be monitored via a sliding window;

a driver to shift the sliding window through a progression of the plurality of processes;

a mapper to map memory corresponding to a portion of the plurality of processes within the sliding window to a virtual address space; and

a workload executor to execute a scan of the mapped memory, at least one of the process selector, the driver, or the mapper implemented via a logic circuit.

9. An apparatus as defined in claim 8 , further including a condition selector to define a condition to determine an aspect of a first one of the plurality of processes to be mapped to the virtual address space.

10. An apparatus as defined in claim 8 , further including a window size definer to select a window size to define the sliding window.

11. An apparatus as defined in claim 8 , wherein the workload executor is implemented via a graphics processing unit.

12. An apparatus as defined in claim 11 , further including a verifier to verify a match found by the scan of the mapped memory executed by the workload executor.

13. An apparatus as defined in claim 8 , wherein the driver is to shift the sliding window through the progression of the plurality of processes by shifting the sliding window after the memory of a current iteration is mapped to the virtual address space.

14. An apparatus as defined in claim 8 , further including a user-mode client, and wherein the virtual address space corresponds to the user-mode client.

15. A tangible computer readable storage medium comprising instructions that, when executed, cause a machine to at least:

select a plurality of processes to be monitored via a sliding window;

shift the sliding window through a progression of the plurality of processes;

map memory corresponding to one of the plurality of processes within the sliding window to a virtual address space; and

execute a scan of the mapped memory.

16. A storage medium as defined in claim 15 , wherein the instructions, when executed, cause the machine to define a condition to determine an aspect of a first one of the plurality of processes to be mapped to the virtual address space.

17. A storage medium as defined in claim 15 , wherein the instructions, when executed, cause the machine to select a window size to define the sliding window.

18. A storage medium as defined in claim 15 , wherein the instructions, when executed, cause the machine to offload the scan of the mapped memory to a graphics processing unit.

19. A storage medium as defined in claim 18 , wherein the instructions, when executed, cause the machine to verify a match found by the scan of the mapped memory.

20. A storage medium as defined in claim 15 , wherein the instructions, when executed, cause the machine to shift the sliding window through the progression of the plurality of processes by shifting the sliding window after the memory of a current iteration is mapped to the virtual address space.

21. A storage medium as defined in claim 15 , wherein the virtual address space corresponds to a user-mode client of the machine.

Assignments (11)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE PATENT TITLES AND REMOVE DUPLICATES IN THE SCHEDULE PREVIOUSLY RECORDED AT REEL: 059354 FRAME: 0335. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 23, 2022
From: MCAFEE, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 060792/0307 →
SECURITY INTEREST Recorded Mar 3, 2022
From: MCAFEE, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT AND COLLATERAL AGENT
Reel/Frame 059354/0335 →
RELEASE OF INTELLECTUAL PROPERTY COLLATERAL - REEL/FRAME 045056/0676 Recorded Mar 2, 2022
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MCAFEE, LLC
Reel/Frame 059354/0213 →
RELEASE OF INTELLECTUAL PROPERTY COLLATERAL - REEL/FRAME 045055/0786 Recorded Oct 26, 2020
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MCAFEE, LLC
Reel/Frame 054238/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENT 6336186 PREVIOUSLY RECORDED ON REEL 045056 FRAME 0676. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Oct 22, 2020
From: MCAFEE, LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 054206/0593 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENT 6336186 PREVIOUSLY RECORDED ON REEL 045055 FRAME 786. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Oct 22, 2020
From: MCAFEE, LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 055854/0047 →
SECURITY INTEREST Recorded Jan 12, 2018
From: MCAFEE, LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 045056/0676 →
SECURITY INTEREST Recorded Jan 12, 2018
From: MCAFEE, LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 045055/0786 →
CHANGE OF NAME AND ENTITY CONVERSION Recorded Aug 24, 2017
From: MCAFEE, INC.
To: MCAFEE, LLC
Reel/Frame 043665/0918 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 16, 2015
From: SURPRISE, JASON M.; DUNBAR, ADRIAN M.M.T.; SAXENA, PARITOSH; TRIANTAFILLOU, NICHOLAS D.; VEMBU, BALAJI; DEWAN, PRASHANT
To: MCAFEE, INC.
Reel/Frame 036807/0648 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2015
From: CABLAO, DEBRA; DURHAM, DAVID MICHAEL; HUGHES, MICHAEL S.; SCHMUGAR, CRAIG D.; TEDDY, JOHN
To: MCAFEE, INC.
Reel/Frame 035921/0500 →