Enhancement mode inverter with variable thickness dielectric stack
View Patent ↗An enhancement-mode inverter includes a load transistor and a drive transistor. The load transistor has a bottom gate architecture with a first source, a first drain, a load channel region, a first semiconductor layer, and a first gate electrode. A load gate dielectric is in the load channel region, and has a load dielectric thickness. The drive transistor has a bottom gate architecture with a second source, a second drain, a drive channel region, a second semiconductor layer, and a second gate electrode. A drive gate dielectric is in the drive channel region, and has a drive dielectric thickness less than the load dielectric thickness. The first source is electrically connected to the second drain and the first gate is electrically connected to the first drain. The load gate dielectric and the drive gate dielectric are part of a common shared dielectric stack.
1. An enhancement-mode inverter comprising:
a load transistor having a bottom gate architecture with a first source, a first drain, a load channel region, a load gate dielectric in the load channel region having a load dielectric thickness, a first semiconductor layer, and a first gate electrode; and
a drive transistor having a bottom gate architecture with a second source, a second drain, a drive channel region, a drive gate dielectric in the drive channel region having a drive dielectric thickness less than the load dielectric thickness, a second semiconductor layer and a second gate electrode;
wherein the first source is electrically connected to the second drain and the first gate is electrically connected to the first drain, and wherein the load gate dielectric and the drive gate dielectric are part of a common shared dielectric stack having a plurality of layers, and wherein each of the plurality of layers of the common shared dielectric stack is continuous over the first gate electrode, and the load dielectric thickness is equal to the thickness of the common shared dielectric stack, and wherein one of the plurality of layers has a different pattern than another of the plurality of layers including a portion which is discontinuous over the second gate so that the drive dielectric thickness is less than the thickness of the common shared dielectric stack.
2. The inverter of claim 1 , wherein the first semiconductor layer and the second semiconductor layer have the same material composition.
3. The inverter of claim 2 , wherein the first semiconductor layer and second semiconductor layer are part of a common semiconductor layer.
4. The inverter of claim 1 , wherein the load transistor and the drive transistor are n-type enhancement-mode transistors.
5. The inverter of claim 4 , wherein the n-type enhancement-mode transistors are metal oxide thin film transistors.
6. The inverter of claim 1 , wherein each of the plurality of layers of the common shared dielectric stack has the same material composition.
7. The inverter of claim 6 , wherein there is an interface region between each of the layers of the plurality of layers.
8. The inverter of claim 1 , wherein one of the plurality of layers includes a different material than another of the plurality of layers.
9. The transistor of claim 1 , wherein the one of the plurality of layers having a different pattern is in contact with the second semiconductor layer has the same pattern over the substrate as the second semiconductor layer and is aligned with the second semiconductor layer.
10. The inverter of claim 1 , wherein the first gate and the second gate are part of a common first electrically conductive layer.
11. The inverter of claim 1 , wherein the first source, the first drain, the second source, and the second drain are part of a common second electrically conductive layer.
12. The inverter of claim 5 , wherein at least one of the first semiconductor layer and the second semiconductor layer is a ZnO-based semiconductor.