Electrically reconfigurable interposer with built-in resistive memory

1. An integrated interposer, comprising:

a substrate;

at least one resistive-type non-volatile memory (NVM) array;

a contact layer on a first surface of the substrate including interconnections configured to couple the at least one resistive-type NVM array to at least one die, the at least one resistive-type NVM array being at least partially embedded within the contact layer of the integrated interposer; and

peripheral circuitry embedded within the integrated interposer and configured to control access to/from the at least one resistive-type NVM array.

2. An integrated interposer, comprising:

a semiconductor substrate,

at least one resistive-type non-volatile memory (NVM) array;

a contact layer on a first surface of the substrate including interconnections configured to couple the at least one resistive-type NVM array to at least one die, the at least one resistive-type NVM array being at least partially embedded within the contact layer of the integrated interposer; and

peripheral circuitry within the semiconductor substrate, the peripheral circuitry configured to control access to/from the at least one resistive-type NVM array.

3. The integrated interposer of claim 1 , in which the substrate comprises a glass substrate and the peripheral circuitry comprises thin film transistors (TFTs) and/or thin film diodes on the first surface of the glass substrate.

4. The integrated interposer of claim 1 , in which the substrate comprises a glass substrate and the peripheral circuitry comprises multi-layer thin film devices supported by the glass substrate.

5. The integrated interposer of claim 1 , in which the at least one resistive-type NVM array is configured to control the interconnections within the contact layer of the integrated interposer.

6. The integrated interposer of claim 1 , in which the at least one resistive-type NVM array is field reconfigurable to selectively couple at least a first die and a second die to a bus within the contact layer of the integrated interposer.

7. The integrated interposer of claim 1 , in which the at least one resistive-type NVM array comprises resistive memory.

8. The integrated interposer of claim 1 , in which the at least one resistive-type NVM array stores device configuration data.

9. The integrated interposer of claim 1 integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

10. A system on chip (SOC), comprising:

an interposer;

at least one resistive-type non-volatile memory (NVM) array at least partially embedded within the interposer; and

interconnections within the interposer coupling the at least one resistive-type NVM array to at least one die, in which the at least one resistive-type NVM array is field reconfigurable to selectively couple at least a first die and a second die to a die-to-die bus within the interposer.

11. The SOC of claim 10 , further comprising a contact layer on a surface of an interposer substrate, in which the at least one resistive-type NVM array is embedded within the contact layer and configurable to control the interconnections within the contact layer.

12. The SOC of claim 10 , in which the at least one resistive-type NVM array comprises resistive memory.

13. The SOC of claim 10 , in which the at least one resistive-type NVM array stores device configuration data.

14. The SOC of claim 10 , further comprising peripheral circuitry configured to control access to/from the at least one resistive-type NVM array.

15. The SOC of claim 10 integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

16. An integrated interposer, comprising:

a substrate;

at least one resistive-type non-volatile memory (NVM) array;

means for interconnecting the at least one resistive-type NVM array to at least one die, the at least one resistive-type NVM array being at least partially embedded within the interconnecting means, the substrate supporting the interconnecting means, in which the at least one resistive-type NVM array is field reconfigurable to selectively couple at least a first die and a second die to a die-to-die bus within the interposer.

17. The integrated interposer of claim 16 , integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.