IP Library Granted Patent US 9,286,833
Granted Patent B2
US 9,286,833 · App. 14/528,421 · Granted Mar 15, 2016

Buffer circuit, scanning circuit, display device, and electronic equipment

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Quick Facts
Patent No.
US 9,286,833
App. No.
14/528,421
Granted
Mar 15, 2016
Kind
B2
Abstract

A buffer circuit includes a first transistor circuit having a first conductivity type transistor, a second transistor circuit having a second conductivity type transistors, in which the first and second transistor circuits are serially connected between a first fixed power supply and a second fixed power supply, and input terminals and output terminals of each of the first and second transistor circuits are connected in common respectively, in which at least one transistor circuit of the first transistor circuit and the second transistor circuit is a double gate transistor, and in which wherein a switch element, when any one transistor circuit of the first and the second transistor circuits is in an operating state, is included to supply a voltage of a third fixed power supply to a common connection node of the double gate transistor of the other transistor circuit.

Claims (34)

1. A display device comprising:

a pixel array section including a plurality of pixels respectively including an electro-optic element; and

a scanning circuit that scans the plurality of pixels and has a buffer circuit in an output stage,

wherein the buffer circuit includes a first transistor circuit and a second transistor circuit,

wherein the first and second transistor circuits are serially connected between a first fixed power supply and a second fixed power supply, and input terminals and output terminals of each of the first and second transistor circuits are connected in common respectively,

wherein at least one transistor circuit of the first transistor circuit and the second transistor circuit is a double gate transistor, and

wherein a switch element, when any one transistor circuit of the first and the second transistor circuits is in an operating state, is comprised to supply a voltage of a third fixed power supply to a common connection node of the double gate transistor of the other transistor circuit.

2. The display device according to claim 1 , wherein a voltage between the first fixed power supply and the third fixed power supply, and a voltage between the third fixed power supply and the second fixed power supply are voltages within a range of a source-drain breakdown voltage of each of the transistors which is included in the first and the second transistor circuits.

3. The display device according to claim 1 , wherein a voltage of the third fixed power supply is a value between the voltages of the first fixed power supply and the second fixed power supply.

4. The display device according to claim 3 , wherein a voltage of the third fixed power supply is an average value of the voltages of the first fixed power supply and the second fixed power supply.

5. The display device according to claim 1 , wherein a voltage of the first fixed power supply is higher than a voltage of a higher voltage side of input voltages applied to the input terminal, and a voltage of the second fixed power supply is lower than a voltage of a lower voltage side of the input voltages.

6. The display device according to claim 1 , wherein the switch element is a transistor having the same conductive type as another transistor circuit which forms an inverter circuit.

7. The display device according to claim 6 , wherein the transistor of the same conductive type has a gate electrode connected to an output terminal.

8. The display device according to claim 1 , wherein

the first transistor circuit includes a first and a second P channel transistors of double gate structure which are connected to the input terminal and the gate electrodes thereof being connected in common,

the first P channel transistor has a source electrode being connected to the first fixed power supply,

the second P channel transistor has a drain electrode being connected to the output terminal, and

a drain electrode of the first P channel transistor and a source electrode of the second P channel transistor are connected to each other in common to be the common connection node, and the voltage of the third fixed power supply is supplied to the common connection node by the switch element.

9. The display device according to claim 1 , wherein

the second transistor circuit includes the first and second N channel transistors of double gate structure which are connected to the input terminal, and the gate electrodes thereof being connected in common,

the first N channel transistor has a drain electrode being connected to the output terminal,

the second N channel transistor has a source electrode being connected to the second fixed power supply,

a source electrode of the first N channel transistor and a drain electrode of the second N channel transistor are connected to each other in common to be the common connection node, and the voltage of the third fixed power supply is supplied to the common connection node by the switch element.

10. The display device according to claim 1 , wherein the output terminal is connected to an inverter circuit of a final stage.

11. The display device according to claim 10 , wherein a voltage of the first fixed power supply is higher than a voltage of a positive side power supply of the inverter circuit of the final stage, and a voltage of the second fixed power supply is lower than a voltage of a negative side power supply of the inverter circuit of the final stage.

12. The display device according to claim 1 , wherein the first and second transistor circuits are directly connected each other.

13. The display device according to claim 1 , wherein the first and second transistor circuits are electrically connected each other.

14. An electronic equipment including a display device according to claim 1 .

15. The electronic equipment according to claim 14 , wherein a voltage between the first fixed power supply and the third fixed power supply, and a voltage between the third fixed power supply and the second fixed power supply are voltages within a range of a source-drain breakdown voltage of each of the transistors which is included in the first and the second transistor circuits.

16. The electronic equipment according to claim 14 , wherein a voltage of the third fixed power supply is a value between the voltages of the first fixed power supply and the second fixed power supply.

17. The electronic equipment according to claim 16 , wherein a voltage of the third fixed power supply is an average value of the voltages of the first fixed power supply and the second fixed power supply.

18. The electronic equipment according to claim 14 , wherein a voltage of the first fixed power supply is higher than a voltage of a higher voltage side of input voltages applied to the input terminal, and a voltage of the second fixed power supply is lower than a voltage of a lower voltage side of the input voltages.

19. The electronic equipment according to claim 14 , wherein the switch element is a transistor having the same conductive type as another transistor circuit which forms an inverter circuit.

20. The electronic equipment according to claim 19 , wherein the transistor of the same conductive type has a gate electrode connected to an output terminal.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2015
From: SONY CORPORATION
To: JOLED INC.
Reel/Frame 036090/0968 →