Method of chip positioning for multi-chip packaging
View Patent ↗Embodiments of the present invention include a method for multi-chip packaging. For example, the method includes positioning a first integrated circuit (IC) on a substrate package based on a first set of reference markers in physical contact with the substrate package and confirming an alignment of the first IC based on a second set of reference markers in physical contact with the substrate package. A second IC is stacked onto first IC based on the first set of reference markers. An alignment of the second IC is confirmed based on the second set of reference markers, where the second set of reference markers is disposed at a different location on the substrate package than the first set of reference markers.
1. A method for multi-chip packaging, the method comprising:
positioning a first integrated circuit (IC) on a substrate package based on a first set of reference markers in physical contact with the substrate package;
confirming a first alignment of the first IC based on a second set of reference markers in physical contact with the substrate package and at a different location on the substrate package than the first set of reference markers;
positioning a second IC on the substrate package based on the first set of reference markers, wherein the second IC is stacked onto the first IC; and
confirming a second alignment of the second IC based on the second set of reference markers.
2. The method of claim 1 , wherein the positioning the first IC and the positioning the second IC comprise positioning the first and second ICs in a diagonal stack arrangement, a straight stack arrangement, or a side-by-side arrangement.
3. The method of claim 1 , wherein the first set of reference markers and the second set of reference markers are disposed in a mold cavity surface of the substrate package.
4. The method of claim 1 , wherein the confirming the first alignment and the confirming the second alignment comprise confirming the first alignment and the second alignment with a human eye.
5. The method of claim 4 , wherein at least one reference marker in the second set of reference markers has at least one dimension greater than or equal to 0.15 mm.
6. The method of claim 1 , wherein the confirming the first alignment and the confirming the second alignment comprise confirming the first alignment and second alignment with a scanner.
7. The method of claim 1 , wherein at least one reference marker in the first set of reference markers or the second set of reference markers comprises a triangle-shaped structure, a T-shaped structure, a cross-shaped structure, or an L-shaped structure.
8. The method of claim 1 , farther comprising:
providing a first wire bond between the first IC and the substrate package; and
providing a second wire bond between the second IC and the substrate package.
9. The method of claim 1 , wherein the substrate package comprises a lead frame package, a small-outline integrated circuit (SOIC) package, or a ball grid array (BGA) package.
10. A method for multi-chip packaging, the method comprising:
placing a first set of reference markers and a second set of reference markers in physical contact with a substrate;
confirming a first alignment of a first integrated circuit (IC) placed on the substrate based on the first set of reference markers; and
confirming a second alignment of a second IC stacked on the first IC based on the second set of reference markers.
11. The method of claim 10 , wherein the first set of reference markers and the second set of reference markers are disposed in a mold cavity surface of the substrate.
12. The method of claim 10 , wherein the confirming the first alignment and the confirming the second alignment comprise confirming the first alignment and the second alignment with a human eye, a scanner, or both.
13. The method of claim 10 , wherein at least one reference marker in the first set of reference markers or the second set of reference markers comprises a triangle-shaped structure, a T-shaped structure, a cross-shaped structure, or an L-shaped structure.
14. The method of claim 10 , further comprising:
providing a first wire bond between the first IC and the substrate; and
providing a second wire bond between the second IC and the substrate.
15. The method of claim 10 , wherein the substrate comprises a lead frame package, a small-outline integrated circuit (SOIC) package, or a ball grid array (BOA) package.