Method and apparatus use with interrupts

1. A method, comprising:

capturing a set of interrupts;

processing interrupts of said set of interrupts, wherein said processing includes determining at least one Hamming Distance between two interrupts of the set of interrupts;

outputting serially said processed interrupts of said set of interrupts onto a shared interconnect for routing to at least one destination of a plurality of destinations; and

based on the at least one Hamming Distance, determining if all of said interrupts of said captured set of interrupts which are to be output onto said shared interconnect have been output onto said shared interconnect before processing another set of captured interrupts.

2. The method as claimed in claim 1 , wherein said outputting includes:

outputting only active interrupts, wherein active interrupts are interrupts that have been actively asserted or de-asserted by a peripheral device onto said shared interconnect.

3. The method as claimed in claim 1 , comprising:

updating an interrupt status register each time an interrupt is processed.

4. The method as claimed in claim 1 , comprising:

concurrent with said processing, capturing a second set of interrupts.

5. The method as claimed in claim 1 , wherein processing said interrupts comprises:

packetizing each interrupt before outputting said interrupt serially onto said shared interconnect.

6. The method as claimed in claim 5 , wherein said packetizing each interrupt comprises:

providing information about one or more of: a type of said interrupt, a destination of said interrupt, and an interrupt level of said interrupt.

7. The method as claimed in claim 5 , wherein said packetizing each interrupt comprises:

providing information associated with routing said interrupt over said shared interconnect.

8. The method as claimed in claim 1 , wherein said outputting serially interrupts of said set of interrupts onto the shared interconnect includes outputting serially interrupts of said set of interrupts onto a network on chip.

9. The method as claimed in claim 1 , comprising:

routing said interrupts of said set of interrupts via said shared interconnect to a destination.

10. The method as claimed in claim 5 , comprising:

de-packetizing each of said packetized interrupts at said destination.

11. An apparatus, comprising:

capture circuitry configured to capture a set of interrupts;

processing circuitry configured to process interrupts of said set of interrupts, wherein said processin includes determining at least one Hamming Distance between two interrupts of the set of interrupts; and

output circuitry configured to output serially said processed interrupts of said set of interrupts onto a shared interconnect for routing to at least one destination of a plurality of destinations,

wherein based on the at least one Hamming Distance, said processing circuitry is configured to determine if all of said interrupts of said captured set of interrupts which are to be output onto said shared interconnect have been output by said output circuitry before processing interrupts of another set of captured interrupts.

12. The apparatus as claimed in claim 11 , comprising:

a circuit configured to detect active interrupts; and

a circuit configured to permit outputting only active interrupts onto said shared interconnect.

13. The apparatus as claimed in claim 11 , wherein said processing circuitry comprises:

an interrupt status register, said processing circuitry configured to update said interrupt status register each time an interrupt is processed.

14. The apparatus as claimed in claim 11 , wherein said processing circuitry is configured to process interrupts of a first set of interrupts concurrent with capture circuitry capturing interrupts of a second set of interrupts.

15. The apparatus as claimed in claim 11 , wherein said processing circuitry is configured to packetize each interrupt before said output circuitry outputs said interrupt serially onto said shared interconnect.

16. The apparatus as claimed in claim 15 , wherein said processing circuitry configured to packetize each interrupt is further configured to provide information about one or more of: a type of said interrupt, a destination of said interrupt, and an interrupt level of said interrupt.

17. The apparatus as claimed in claim 15 , wherein said processing circuitry configured to packetize each interrupt is further configured to provide information associated with routing said interrupt over said shared interconnect.

18. A system having a plurality of physical units, comprising:

a first physical unit having a destination; and

a second physical unit having:

capture circuitry configured to capture a set of interrupts;

processing circuitry configured to process interrupts of said set of interrupts, wherein said processing circuitry is arranged to determine at least one Hamming Distance between two interrupts of the set of interrupts; and

output circuitry configured to output serially said processed interrupts of said set of interrupts onto a shared interconnect for routing to at least one destination of a plurality of destinations, at least one interrupt directed to said destination of the first physical unit,

wherein based on the at least one Hamming Distance, said processing circuitry is configured to determine if all of said interrupts of said captured set of interrupts which are to be output onto said shared interconnect have been output by said output circuitry before processing interrupts of another set of captured interrupts.

19. The system as claimed in claim 18 , wherein said shared interconnect includes at least one network on chip.

20. The system as claimed in claim 18 , said second physical unit comprising:

processing circuitry configured to packetize each interrupt before said output circuitry outputs said interrupt serially onto said shared interconnect.

21. The system as claimed in claim 18 , wherein said processing circuitry of said second physical unit is configured to distinguish between active interrupts and inactive interrupts.