IP Library Granted Patent US 9,245,950
Granted Patent B2
US 9,245,950 · App. 14/537,148 · Granted Jan 26, 2016

Method for fabricating an insulated gate bipolar transistor

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Quick Facts
Patent No.
US 9,245,950
App. No.
14/537,148
Granted
Jan 26, 2016
Kind
B2
Abstract

A method for manufacturing a semiconductor device is provided. The semiconductor device includes a cathode region of the diode, a first buffer region adjacent to the cathode region at a rear surface side of a semiconductor substrate, a collector region of the IGBT, and a second buffer region adjacent to the collector region at the rear surface side. The method includes forming the step portion on the front surface so that the thin portion and the thick portion are formed in the semiconductor substrate, and injecting n-type impurities to a range on the front surface extending across the thin and thick portions so that the first buffer region and the second buffer region are formed.

Claims (17)

1. A method for manufacturing a semiconductor device that comprises: a semiconductor substrate in which a diode and an IGBT are formed, wherein

a step portion is formed on a front surface of the semiconductor substrate so that a thin portion and a thick portion thicker than the thin portion are formed in the semiconductor substrate, and

the semiconductor substrate comprises:

an n-type cathode region of the diode formed in a range exposed to the front surface in the thin portion,

an n-type first buffer region having an n-type impurity density lower than that in the cathode region, and adjacent to the cathode region at a rear surface side of the semiconductor substrate in the thin portion,

a collector region of the IGBT being of p-type and formed in a range exposed to the front surface in the thick portion,

an n-type second buffer region adjacent to the collector region at the rear surface side in the thick portion, and

an n-type drift region having an n-type impurity density lower than those of the first and second buffer regions, and adjacent to the first and second buffer regions at the rear surface side in the thin and thick portions,

the method comprising:

forming the step portion on the front surface so that the thin portion and the thick portion are formed in the semiconductor substrate; and

injecting n-type impurities to a range on the front surface extending across the thin and thick portions so that the first buffer region and the second buffer region are formed.

2. A method of claim 1 , wherein a boundary plane between the thin portion and the thick portion is a boundary plane of the diode and the IGBT.

3. A method of claim 2 , wherein

the step portion comprises two lateral surfaces facing each other,

a width between the two lateral surfaces in a direction perpendicular to the boundary plane increases toward the front surface of the thick portion, and

an electrode is formed on the front surface of the thin portion and the two lateral surfaces.

4. A method of claim 1 , further comprising forming an insulating film on a lateral surface of the step portion.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2020
From: TOYOTA JIDOSHA KABUSHIKI KAISHA
To: DENSO CORPORATION
Reel/Frame 052285/0419 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: KAMIJO, TAKUMA
To: TOYOTA JIDOSHA KABUSHIKI KAISHA
Reel/Frame 034136/0844 →