Power architecture for low power modes in storage devices
View Patent ↗A power control device comprising an always-on-domain (AOD) which includes control logic circuitry for controlling power from a power source, load switches, bias current generators. The power control device also includes, outside of the AOD, functional blocks. The control logic circuitry is configured to receive a signal to go into a lower power state, initiate a shut-down sequence of the load switches and the bias current generators of the AOD, to disable circuitry outside of the AOD, including the functional blocks of the power control device and loads controlled by the power control device, and operate in a low power state to detect a wake-up signal. The shut-down sequence may additionally include sequencing off voltage regulators outside of the AOD and a clock control inside the AOD.
1. A power control device comprising:
an always-on-domain (AOD) comprising:
control logic circuitry for controlling power from a power source;
a plurality of load switches; and
a plurality of bias current generators; and
a plurality of functional blocks,
wherein the control logic circuitry is configured to:
receive a signal to go into a lower power state;
initiate a shut-down sequence of the load switches and the bias current generators of the AOD, to disable circuitry outside of the AOD, including the functional blocks of the power control device and loads controlled by the power control device; and
operate in a low power state to detect a wake-up signal.
2. The power control device as recited in claim 1 , wherein the power control device is in a data storage device and the signal and the power source are from a host coupled to the data storage device.
3. The power control device as recited in claim 2 , wherein the control logic circuitry is coupled to a controller in the data storage device.
4. The power control device as recited in claim 3 , wherein the control logic circuitry is further configured to:
upon receiving the signal from the host indicating a first type of transition to a lower power state,
send a signal to the controller to cause the controller to initiate one or more operations to prepare the data storage device to enter into the low power state;
await an input signal from the controller that the operations are complete; and
initiate the shut-down sequence after receiving the input signal from the controller.
5. The power control device as recited in claim 4 , wherein the control logic circuitry is further configured to:
upon receiving the signal from the host indicating a second type of transition to a lower power state,
initiate the shut-down sequence without waiting for an input signal from the controller.
6. The power control device as recited in claim 1 , wherein the AOD further comprises a plurality of clocks and the shut-down sequence additionally includes sequencing off the clocks.
7. The power control device as recited in claim 6 , further comprising a plurality of voltage regulators outside of the AOD, wherein the shut-down sequence additionally includes sequencing off the plurality of voltage regulators outside of the AOD.
8. The power control device as recited in claim 7 , further the control logic circuitry is further configured to perform shut-down sequence by:
sequencing off the regulators;
sequencing off the clocks;
sequencing off the load switches; and
sequencing off the bias current generators.
9. The power control device as recited in claim 1 , further the control logic circuitry is further configured to:
detect a wake-up signal; and
initiate a start-up sequence of the load switches and the bias current generators of the AOD, to enable circuitry outside of the AOD, including the functional blocks of the power control device and loads controlled by the power control device.
10. An integrated circuit comprising the power control device as recited in claim 1 .
11. A data storage device comprising the power control device as recited in claim 1 .
12. A method for operating a power control device comprising an always-on-domain (AOD) that includes for control logic circuitry controlling power from a power source, a plurality of load switches and a plurality of bias current generators; and
a plurality of functional blocks, the method comprising:
receiving a signal to go into a lower power state;
initiating a shut-down sequence of the load switches and the bias current generators of the AOD, to disable circuitry outside of the AOD, including the functional blocks of the power control device and loads controlled by the power control device; and
operating in a low power state to detect a wake-up signal wherein the method is performed by the control logic circuitry of the AOD.
13. The method as recited in claim 12 , wherein the power control device is in a data storage device and the signal and the power source are from a host coupled to the data storage device.
14. The method as recited in claim 13 , wherein the power control device is coupled to a controller in the data storage device.
15. The method as recited in claim 14 , further comprising:
upon receiving the signal from the host indicating a first type of transition to a lower power state,
sending a signal to the controller to cause the controller to initiate one or more operations to prepare the data storage device to enter into the low power state;
awaiting an input signal from the controller that the operations are complete; and
initiating the shut-down sequence after receiving the input signal from the controller.
16. The method as recited in claim 15 , further comprising:
upon receiving the signal from the host indicating a second type of transition to a lower power state,
initiating the shut-down sequence without waiting for an input signal from the controller.
17. The method as recited in claim 12 , wherein the AOD further comprises a plurality of clocks and the shut-down sequence additionally includes sequencing off the clocks.
18. The method as recited in claim 17 , wherein the power control device further comprises a plurality of voltage regulators outside of the AOD, wherein the shut-down sequence additionally includes sequencing off the plurality of voltage regulators outside of the AOD.
19. The method as recited in claim 18 , wherein performing shut-down sequence further comprises:
sequencing off the regulators;
sequencing off the clocks;
sequencing off the load switches; and
sequencing off the bias current generators.
20. The method as recited in claim 12 , further comprising:
detecting a wake-up signal; and
initiating a start-up sequence of the load switches and the bias current generators of the AOD, to enable circuitry outside of the AOD, including the functional blocks of the power control device and loads controlled by the power control device.