Peripheral bus error containment and recovery
View Patent ↗A peripheral bus error containment and recovery system enables a bus device to experience a fatal bus error and recover without stopping execution of an operating system. When a fatal bus error is detected at the bus device, a bus controller may deactivate a data link layer for a downstream port populated by the bus device, causing an operating system device driver to be uninstalled for the bus device. Then, the operating system device driver may be reinstalled without physically removing the bus device.
1. A method for peripheral bus error containment and recovery, comprising:
detecting, at a controller of a peripheral bus included in an information handling system, a fatal device error at a downstream port from the controller, wherein the downstream port is populated by a bus device; and
responsive to detecting the fatal device error:
deactivating a data link layer for the downstream port; and
setting a presence detect state bit to zero for the bus device, wherein a first interrupt is generated for the downstream port to an operating system executing on the information handling system, the first interrupt causing the operating system to remove a device driver for the bus device.
2. The method of claim 1 , further comprising:
after a delay period after the presence detect state bit is set to zero, setting the presence detect state bit to one, wherein a second interrupt is generated for the downstream port to the operating system, the second interrupt causing the operating system to install the device driver for the bus device.
3. The method of claim 1 , wherein the peripheral bus is a peripheral component interconnect bus.
4. The method of claim 3 , wherein the peripheral component interconnect bus is a peripheral component interconnect express bus.
5. The method of claim 1 , further comprising:
when the presence detect state bit is set to zero, causing a presence detect changed bit to be set to one, wherein the presence detect changed bit triggers the first interrupt.
6. The method of claim 2 , further comprising:
when the presence detect state bit is set to one, causing a presence detect changed bit to be set to one, wherein the presence detect changed bit triggers the second interrupt.
7. The method of claim 1 , wherein the controller is included in at least one of: a root complex and a bus switch.
8. An information handling system for peripheral bus error containment and recovery comprising:
a bus controller electronically coupled to a peripheral bus, the bus controller to:
detect a fatal device error at a downstream port of the peripheral bus, wherein the downstream port is populated by a bus device, and wherein the peripheral bus is included in an information handling system; and
responsive to detecting the fatal device error:
deactivate a data link layer for the downstream port; and
set a presence detect state bit to zero for the bus device, wherein a first interrupt is generated for the downstream port to an operating system executing on the information handling system, the first interrupt causing the operating system to remove a device driver for the bus device.
9. The information handling system of claim 8 , wherein the bus controller is further to:
after a delay period after the presence detect state bit is set to zero, set the presence detect state bit to one, wherein a second interrupt is generated for the downstream port to the operating system, the second interrupt causing the operating system to install the device driver for the bus device.
10. The information handling system of claim 8 , wherein the peripheral bus is a peripheral component interconnect bus.
11. The information handling system of claim 10 , wherein the peripheral component interconnect bus is a peripheral component interconnect express bus.
12. The information handling system of claim 8 , wherein the bus controller is further to:
when the presence detect state bit is set to zero, cause a presence detect changed bit to be set to one, wherein the presence detect changed bit triggers the first interrupt.
13. The information handling system of claim 9 , wherein the bus controller is further to:
when the presence detect state bit is set to one, cause a presence detect changed bit to be set to one, wherein the presence detect changed bit triggers the second interrupt.
14. The information handling system of claim 8 , wherein the bus controller is included in at least one of: a root complex and a bus switch.
15. A bus controller for peripheral bus error containment and recovery, the bus controller to:
detect a fatal device error at a downstream port of the bus controller, wherein the downstream port is populated by a bus device, and wherein the bus controller is included in the information handling system; and
responsive to detecting the fatal device error:
deactivate a data link layer for the downstream port; and
set a presence detect state bit to zero for the bus device, wherein a first interrupt is generated for the downstream port to an operating system executing on the information handling system, the first interrupt causing the operating system to remove a device driver for the bus device.
16. The bus controller of claim 15 , further to:
after a delay period after the presence detect state bit is set to zero, set the presence detect state bit to one, wherein a second interrupt is generated for the downstream port to the operating system, the second interrupt causing the operating system to install the device driver for the bus device.
17. The bus controller of claim 15 , wherein the peripheral bus is a peripheral component interconnect bus.
18. The bus controller of claim 17 , wherein the peripheral component interconnect bus is a peripheral component interconnect express bus.
19. The bus controller of claim 15 , further to:
when the presence detect state bit is set to zero, cause a presence detect changed bit to be set to one, wherein the presence detect changed bit triggers the first interrupt.
20. The bus controller of claim 16 , further to:
when the presence detect state bit is set to one, cause a presence detect changed bit to be set to one, wherein the presence detect changed bit triggers the second interrupt.
21. The bus controller of claim 17 , wherein the bus controller is included in at least one of: a root complex and a bus switch.