System, method and recording medium for analog to digital converter calibration
View Patent ↗A calibration system for an analog-to-digital converter (ADC) an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.
1. A calibration method for an analog-to-digital converter (ADC), the method comprising:
receiving an analog input;
converting the analog input to digital multi-bit data at the ADC;
receiving, at the ADC, a training signal where the statistics of the signal are known and cause states of the ADC to experience transitions over time;
measuring an amplitude based on the digital multi-bit data; and
adjusting a calibration circuit of the ADC based on the amplitude.
2. The calibration method of claim 1 , wherein the adjusting the calibration circuit changes an offset of the ADC.
3. The calibration method of claim 1 , wherein the measuring is implemented in conjunction with a power meter that estimates an output power of the ADC by sub-sampling an output of the ADC.
4. The calibration method of claim 1 , wherein the method is performed with calibration logic implemented as an off-chip architecture.
5. The calibration method of claim 1 , wherein the analog input is received from a noise source.
6. The calibration method of claim 5 , wherein the noise source is a loop filter.
7. The calibration method of claim 1 , wherein the method is performed with calibration logic implemented as an on-chip architecture.
8. An apparatus that performs a calibration method for an analog-to-digital converter (ADC), the apparatus comprising:
means for converting an analog input to digital multi-bit data and for receiving a training signal where the statistics of the signal are known and cause states of the means for converting to experience transitions over time;
means for measuring an amplitude based on the digital multi-bit data; and
means for adjusting the means for converting, based on the amplitude.
9. The apparatus of claim 8 , wherein the means for adjusting changes an offset of the means for converting.
10. The apparatus of claim 8 , wherein the means for measuring is implemented in conjunction with means for estimating an output power of the ADC by sub-sampling an output of the means for converting.
11. The apparatus of claim 8 , wherein the means for adjusting is implemented as an off-chip architecture.
12. The apparatus of claim 8 , wherein the means for converting receives the analog input from means for providing noise.
13. An apparatus that performs a calibration, the apparatus comprising:
an analog-to-digital converter (ADC) that converts an analog input to digital multi-bit data and receives a training signal, wherein statistics of the training signal are known, and the training signal causes states of the ADC to experience transitions over time;
a calibration circuit that calibrates a plurality of comparators of the ADC;
a digital block that measures an amplitude of the digital multi-bit data; and
calibration logic configured to control the calibration circuit, based on the amplitude.
14. The apparatus of claim 13 , wherein the calibration logic changes an offset of the ADC.
15. The apparatus of claim 13 , wherein the digital block is implemented in conjunction with a power meter that estimates an output power of the ADC by sub-sampling an output of the ADC.
16. The apparatus of claim 13 , wherein the calibration logic is implemented as an off-chip architecture.
17. The apparatus of claim 13 , wherein the ADC receives the analog input from a noise source.
18. The apparatus of claim 13 , wherein an output of the digital block includes at least one of a root mean square of the amplitude of the digital multi-bit data and a mean of the amplitude of the digital multi-bit data.