Generating signals with accurate quarter-cycle intervals using digital delay locked loop

1. An apparatus comprising:

a delay circuit configured to generate a plurality of intermediate signals in response to (i) a clock signal and (ii) an adjustment signal; and

a control circuit configured to generate said adjustment signal and a plurality of output signals having a quarter-cycle interval in response to (i) said plurality of intermediate signals and (ii) said clock signal, wherein (A) said delay circuit comprises a delay stage comprising (a) a course delay adjustment stage and (b) a fine delay adjustment stage and (B) said fine delay adjustment stage (i) comprises a coarse delay cell and an interpolation circuit and (ii) is configured to implement a fine delay adjustment for said intermediate signals based on an interpolation of a coarse delay adjustment for said intermediate signals by said coarse delay adjustment stage.

2. The apparatus according to claim 1 , wherein said clock signal comprises a reference clock oscillating at a fixed frequency.

3. The apparatus according to claim 1 , wherein said control circuit comprises:

a compensation stage configured to generate said plurality of output signals having less intrinsic delay than said plurality of intermediate signals.

4. The apparatus according to claim 3 , wherein said compensation stage passes through said plurality of intermediate signals and an inverted version of said clock signal.

5. The apparatus according to claim 4 , wherein said control circuit further comprises:

said compensation stage to compensate for intrinsic delays of interpolation circuits.

6. The apparatus of claim 1 , wherein said control circuit further comprises:

a comparison circuit to compare the output from a last of a plurality of delay stages to a delayed version of the clock signal;

a first locking circuit to lock the output from the last delay stage to the delayed version of the clock signal with coarse delay adjustment only; and

a second locking circuit to lock the output from the last delay stage to the delayed version of the clock signal with both coarse delay adjustment and fine delay adjustment.

7. The apparatus of claim 6 , wherein the comparison circuit comprises a phase detector.

8. The apparatus of claim 7 , wherein the first locking circuit comprises a first finite state machine and the second locking circuit comprises a second finite state machine.

9. The apparatus of claim 1 , wherein the delay circuit comprises multiple delay stages in series.

10. The apparatus of claim 1 , wherein the coarse delay adjustment stage comprises a plurality of coarse delay cells configured in series.

11. The apparatus of claim 1 , wherein the control circuit further comprises a compensation circuit, said compensation circuit comprising multiple interpolation cells configured in parallel.

12. The apparatus of claim 11 , wherein the compensation circuit comprises multiple replicas of interpolation circuits.

13. A method for generating four output signals with accurate quarter-cycle intervals, the method comprising:

receiving a reference clock signal;

generating intermediate clock signals in each of a plurality of delay stages connected in series in response to said reference clock signal and an adjustment signal, wherein (A) each delay stage comprises (i) a course delay stage and (ii) a fine delay stage and (B) said fine delay stage (i) comprises a coarse delay cell and an interpolation circuit and (ii) is configured to implement a fine delay adjustment for said intermediate signals based on an interpolation of a coarse delay adjustment for said intermediate signals by said course delay stage;

comparing the intermediate signal of a last delay stage of the plurality of delay stages with a delayed version of the reference clock signal;

detecting whether a feedback loop is in lock with said delayed version of the reference clock signal;

adjusting the delay stages; and

compensating of the four output signals based on said adjustment signal applied to each delay stage.

14. The method of claim 13 , wherein comparison of the intermediate signal of the last delay stage with the delayed version of the reference clock signal comprises:

a phase detector having a first input, a second input, a third input, a first output and a second output, wherein the first input is the delayed version of the reference clock signal, the second input is the intermediate signal from a first delay stage, the third input is the intermediate signal from the last delay stage, the first output is to indicate the third input lags the next cycle of the first input and the second output is to indicate the third input leads the next cycle of the first input.

15. The method of claim 13 , wherein:

a) said coarse delay stage has a first input, a second input and an output, wherein the first input is a signal to be delayed, the second input comprises said adjustment signal and the output is a coarse delay output; and

b) said fine stage has a first input, a second input and an output, wherein the first input is the coarse delay output, the second input comprises said adjustment signal and the output is the intermediate signal.

16. The method of claim 15 , wherein adjusting the delay stages comprises a shift register having a first input, a second input, a third input, a fourth input and an output, wherein the first input controls a shifting direction, the second input controls a locking status of the coarse delay stage, the third input controls a locking status of the fine delay stage, the fourth input is a shifting clock, and the output controls the adjustment signal for at least one of the coarse delay stage and the fine delay stage.

17. The method according to claim 16 , wherein (A) said coarse delay stage comprises multiple coarse delay cells in series configured to be selected by the adjustment signal from the shift register and (B) the fine delay stage is adjusted by the adjustment signal from the shift register.

18. The method of claim 16 , wherein detecting the feedback loop comprises:

a) a lock detector having a first input, a second input, a third input, a first output, a second output, a third output and a fourth output, wherein the first input is the reference clock, the second input is the first output from a phase detector, the third input is the second output from the phase detector, the first output shows the direction of the shift register, the second output shows the locking status of the coarse delay stage, the third output shows the locking status of the fine delay stage, and the fourth output gives the shifting clock for the shift register; and

b) a bandwidth adjustment cell which adjusts the loop bandwidth.

19. An apparatus comprising:

a delay circuit configured to generate a plurality of intermediate signals in response to ( 1 ) a clock signal and (ii) an adjustment signal; and

a control circuit (A) comprising a compensation circuit and (B) configured to generate said adjustment signal and a plurality of output signals having a quarter-cycle interval in response to (i) said plurality of intermediate signals and (ii) said clock signal, wherein (A) said delay circuit comprises a fine delay stage configured to implement a fine delay adjustment for said intermediate signals based on an interpolation of a coarse delay adjustment for said intermediate signals by a coarse delay stage of said delay circuit and (B) said compensation circuit comprises (i) multiple interpolation cells configured in parallel and (ii) multiple replicas of interpolation circuits.