Command injection to hardware pipeline for atomic configuration
View Patent ↗A command processing system facilitates pipeline configuration. Each stage of a packet processing pipeline may access certain memory locations for processing of a data packet as it passes through each stage. The command processing system facilitates changing the memory locations in an atomic manner.
1. A system comprising:
a packet processing pipeline configured to process data packets;
a command queue in communication with the packet processing pipeline; and
queue control circuitry in communication with the command queue and the packet processing pipeline, the queue control circuitry configured to:
direct pipeline configuration commands into the command queue; and initiate configuration of the packet processing pipeline by:
directing the pipeline configuration commands into the packet processing pipeline; and
redirecting data packets bound for the packet processing pipeline into the command queue until the pipeline configuration commands have entered the packet processing pipeline.
2. The system of claim 1 , where the queue control circuitry comprises:
a command packet identification output in communication with the packet processing pipeline.
3. The system of claim 2 , where the packet processing pipeline is configured to accept a command identification bit from the command packet identification output, and propagate the command identification bit down the packet processing pipeline.
4. The system of claim 1 , where the queue control circuitry comprises:
a command injection output configured to indicate when to direct the pipeline configuration commands into the command queue.
5. The system of claim 4 , further comprising:
selection logic responsive to the command injection output by directing the pipeline configuration commands into the command queue.
6. The system of claim 1 , where the queue control circuitry comprises:
a command injection output configured to indicate when to redirect the data packets into the command queue.
7. The system of claim 6 , further comprising:
selection logic responsive to the command injection output by redirecting the data packets into the command queue.
8. The system of claim 1 , where the command queue further comprises:
a command queue status output configured to indicate how many pipeline configuration commands are in the command queue.
9. The system of claim 1 , where the queue control circuitry further comprises:
a ‘start execution’ input configured to direct the queue control circuitry to inject the pipeline configuration commands into the packet processing pipeline, instead of the data packets.
10. The system of claim 9 , where the queue control circuitry further comprises:
a ‘ready’ output configured to indicate when additional pipeline configuration commands may be written to the command queue.
11. A system comprising:
a pipeline interface to a packet processing pipeline;
a command queue in communication with the pipeline interface; and
queue control circuitry in communication with the command queue and the pipeline interface, the queue control circuitry configured to:
direct pipeline configuration commands into the command queue; and initiate configuration of the packet processing pipeline by:
directing the pipeline configuration commands through the pipeline interface and into the packet processing pipeline; and
assert a hold signal to ingress logic, the hold signal configured to pause data packets flowing from the ingress logic through the pipeline interface into the packet processing pipeline.
12. The system of claim 11 , where the queue control circuitry comprises:
a command packet identification output in communication with the packet processing pipeline.
13. The system of claim 12 , where the pipeline is configured to accept a command identification bit from the command packet identification output that indicates whether a data packet or a pipeline configuration command is entering the packet processing pipeline.
14. The system of claim 11 , where the queue control circuitry comprises:
a command injection output configured to indicate whether the data packets or the pipeline configuration commands pass through the pipeline interface.
15. The system of claim 14 , further comprising:
selection logic responsive to the command injection output.
16. The system of claim 11 , where the command queue further comprises:
a command queue status output configured to indicate how many pipeline configuration commands are in the command queue.
17. The system of claim 11 , where the queue control circuitry further comprises:
a ‘start execution’ input configured to direct the queue control circuitry to inject the pipeline configuration commands into the packet processing pipeline, instead of the data packets.
18. The system of claim 17 , where the queue control circuitry further comprises:
a ‘ready’ output configured to indicate when additional pipeline configuration commands may be written to the command queue.
19. A system comprising:
a pipeline interface to a packet processing pipeline;
a command queue in communication with the pipeline interface; a data packet input;
a pipeline configuration command input;
queue selection circuitry configured to select between the data packet input and the pipeline configuration command input for passing into the command queue;
entry selection circuitry configured to select between the data packet input and the command queue for passing through the pipeline interface into the packet processing pipeline; and
queue control circuitry in communication with the command queue and the pipeline interface, the queue control circuitry configured to:
initiate configuration of the packet processing pipeline by:
directing the entry selection circuitry to pass pipeline configuration commands provided on the pipeline configuration command input from the command queue through the pipeline interface and into the packet processing pipeline;
assert a hold signal to ingress logic, the hold signal configured to pause data packets flowing from the ingress logic through the pipeline interface into the packet processing pipeline; and
when the command queue is empty, de-assert the hold signal and direct the entry selection circuitry to pass data packets provided on the data packet input through the pipeline interface and into the packet processing pipeline.
20. The system of claim 19 , where the queue control circuitry further comprises:
a command packet identification output in communication with the pipeline interface, where the pipeline interface is configured to accept a command identification bit from the command packet identification output, and provide the command identification bit to the packet processing pipeline.