IP Library Granted Patent US 9,362,287
Granted Patent B2
US 9,362,287 · App. 14/539,410 · Granted Jun 7, 2016

Semiconductor device and method for manufacturing the same

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,362,287
App. No.
14/539,410
Granted
Jun 7, 2016
Kind
B2
Abstract

A semiconductor device includes: a first transistor and a second transistor disposed in or on a silicon substrate; an element isolation structure that isolates the first transistor and the second transistor, the element isolation structure comprising at least one of a first element isolation film disposed in a region of a first well disposed in a formation area of the first transistor, or a second element isolation film disposed in a region of a second well disposed in a formation area of the second transistor, and a third well disposed under the first well in the silicon substrate and is electrically connected to the second well. The first element isolation film or the second element isolation film has a portion that does not extend over a boundary between the first well and the second well.

Claims (27)

1. A semiconductor device comprising:

a first transistor and a second transistor disposed in or on a silicon substrate;

a first well disposed in a formation area of the first transistor, and a second well disposed in a formation area of the second transistor, wherein the second well surrounds the first well in a plan view of the silicon substrate; and

a third well disposed under an entirety of the first well, but less than an entirety of the second well, and wherein the third well is electrically connected to the second well,

wherein the semiconductor device does not include an element isolation structure including an element isolation film disposed in the silicon substrate between the first transistor and the second transistor, and wherein the first transistor is an N-type transistor, the second transistor is a P-type transistor, the first well is a P-well, the second well is an N-well, and the third well is an N-well.

2. The semiconductor device of claim 1 , further comprising at least one of a source or drain region disposed at a boundary between the first well and the second well, or a silicide block film disposed above the boundary.

3. A semiconductor device comprising:

a first transistor in a first well formed by implanting ions of a first type in a substrate;

a second transistor in a second well formed by implanting ions of a second type in the substrate, the second well abutting and surrounding the first well in a plan view of the substrate to form a boundary therebetween;

a third well formed by implanting ions of the second type in the substrate, the third well disposed under an entirety of the first well and extending under less than an entirety of the second well, lowering an electrical resistance of a connection between the third well and the second well; and

a first element isolation structure in a surface of the substrate between the first transistor and the second transistor, wherein the first element isolation structure surrounds the first well, overlies the second well and does not extend over the boundary between the first well and the second well,

wherein the third well extends under and not past the first element isolation structure overlying the second well.

4. The semiconductor device of claim 3 , further comprising a silicide film disposed above the boundary.

5. The semiconductor device of claim 3 , wherein the second well extends deeper into the substrate than the first well, increasing an area of the connection between the third well and the second well.

6. The semiconductor device of claim 3 , further comprising a second element isolation structure overlying the first well and surrounding the first transistor, wherein the second element isolation structure does not extend over the boundary between the first well and the second well.

7. A semiconductor device comprising:

an N-type transistor in a P-well in a substrate;

a P-type transistor in an N-well in the substrate, the N-well abutting and surrounding the P-well in a plan view of the substrate to form a boundary therebetween;

a deep N-well disposed in the substrate under the entire P-well and extending under less than an entirety of the N-well, lowering an electrical resistance of a connection between the deep N-well and the N-well;

a first element isolation structure in a surface of the substrate between the N-type transistor and the P-type transistor, wherein the first element isolation structure surrounds the P-well, overlies the N-well and does not extend over the boundary between the P-well and the N-well; and

a silicide film disposed above the boundary,

wherein the deep N-well extends under and not past the first element isolation structure overlying the N-well.

8. The semiconductor device of claim 7 , further comprising at least one of a source or drain region disposed at the boundary between the N-well and the P-well, and underlying the silicide film disposed above the boundary.

9. The semiconductor device of claim 7 , wherein the N-well extends deeper into the substrate than the P-well, increasing an area of the connection between the deep N-well and the N-well.

10. The semiconductor device of claim 7 , wherein the P-well comprises Boron ions implanted at a first energy, and the N-well comprises Phosphorous ions implanted at a second energy greater than the first energy.

11. The semiconductor device of claim 7 , further comprising a second element isolation structure overlying the P-well and surrounding the N-type transistor, wherein the second element isolation structure does not extend over the boundary between the N-well and the P-well.

12. The semiconductor device of claim 11 , wherein the deep N-well extends under first element isolation structure overlying the N-well.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 12, 2015
From: SPANSION LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 035902/0821 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 12, 2014
From: EGUCHI, AKIRA
To: SPANSION LLC
Reel/Frame 034157/0401 →