Selective layer disordering in III-nitrides with a capping layer
Selective layer disordering in a doped III-nitride superlattice can be achieved by depositing a dielectric capping layer on a portion of the surface of the superlattice and annealing the superlattice to induce disorder of the layer interfaces under the uncapped portion and suppress disorder of the interfaces under the capped portion. The method can be used to create devices, such as optical waveguides, light-emitting diodes, photodetectors, solar cells, modulators, laser, and amplifiers.
1. A method for selective layer disordering in III-nitrides, comprising:
growing a III-nitride superlattice comprising a periodic structure of layers of two or more III-nitride semiconductor materials with different band gaps on a substrate at a growth temperature chosen to prevent layer disordering during growth, wherein one or more of the superlattice layers are doped with an impurity during growth,
depositing a dielectric capping layer on a portion of the surface of the superlattice to provide a capped portion and an uncapped portion, and
annealing the superlattice at an annealing temperature and time sufficient to induce disordering of the superlattice layer interfaces due to diffusion of the impurity under the uncapped portion and suppress disordering of the interfaces under the capped portion.
2. The method of claim 1 , wherein the III-nitride superlattice comprises a plurality of AlGaN/AlN, GaN/AlN, GaN/AlGaN, InGaN/GaN, InGaN/AlN, InGaN/AlGaN, AlInN/GaN, AlInN/AlN, or AlInN/InGaN layers.
3. The method of claim 1 , wherein the impurity comprises silicon, magnesium, selenium, or tellurium.
4. The method of claim 1 , wherein the dopant concentration in the superlattice is greater than 5×10 18 cm −3 .
5. The method of claim 1 , wherein the growing comprises metal-organic vapor phase epitaxy, molecular beam epitaxy, and vapor phase epitaxy.
6. The method of claim 1 , wherein the growth temperature is less than 885° C.
7. The method of claim 1 , wherein the annealing temperature is greater than 700° C.
8. The method of claim 7 , wherein the annealing temperature is greater than 1000° C.
9. The method of claim 1 , wherein the annealing occurs in a carrier gas.
10. The method of claim 9 , wherein the carrier gas comprises N 2 , NH 3 , H 2 , or He.
11. The method of claim 1 , wherein the substrate comprises sapphire, SiC, AlN, GaN, or alloys thereof.
12. The method of claim 11 , wherein the substrate further comprises an intervening template layer having a low dislocation density deposited on the substrate.
13. The method of claim 12 , wherein the template layer comprises AlN, GaN, InGaN, or AlGaN.
14. The method of claim 1 , wherein the dielectric capping layer comprises SiN, SiON, or SiO 2 .
15. The method of claim 1 , wherein the thickness of the layers is less than 10 nanometers.
16. The method of claim 1 , wherein the superlattice has an energy transition and wherein the uncapped portion has an energy transition shifted in wavelength from the capped portion.
17. The method of claim 16 , wherein the energy transition is intersubband and the uncapped portion is shifted to a longer wavelength from the capped portion.
18. The method of claim 16 , wherein the energy transition is interband and the uncapped portion is shifted to a shorter wavelength from the capped portion.