In one or more embodiments, a caching apparatus includes functionality to persist evaluation results associated with pcells in a design across sessions of an EDA application as well as across design libraries. The caching apparatus may create and maintain a mirror cache in a design library with only subMasters referenced by the design library. The contents of a central cache file or a mirror cache in the design library are examined for an evaluation result. If the evaluation result is not found in the central cache file, the evaluation result may be retrieved from the mirror cache if present.
1. A method comprising:
persisting, using one or more computer systems, evaluation results associated with a variant of a parameterized cell at a location in at least one of a central cache file or a mirror cache file in a design library;
mapping, using the one or more computer systems, the variant to the location;
instantiating, using the one or more computer systems, the parameterized cell from either the cache file or the mirrored cache file when the cache file or the mirrored cache file contains the evaluation result; and
synchronizing the evaluation result from the mirror cache file to the central cache file in response to a determination that the central cache file fails to include the evaluation result.
2. The method of claim 1 further comprising synchronizing the evaluation result from the central cache file to the mirror cache file in response to a determination that the mirror cache file fails to include the evaluation result.
3. The method of claim 1 further comprising delaying instantiation of the parameterized cell from an evaluation stage to an instance header binding stage.
4. The method of claim 1 further comprising receiving the evaluation results associated with the parameterized cell in the design from one or more parameterized cell evaluators.
5. The method of claim 1 further comprising:
receiving information associated with the parameterized cell;
performing one or more evaluations to determine the variant; and
generating information associated with the variant.
6. A non-transitory computer-readable medium storing program code executable by one or more processors associated with one or more computer systems, the non-transitory computer-readable medium comprising:
code for persisting evaluation results associated with a variant of a parameterized cell at a location in at least one of a central cache file or a mirror cache file in a design library;
code for mapping the variant to the location;
code for instantiating the parameterized cell from either the cache file or the mirrored cache file when the cache file or the mirrored cache file contains the evaluation result; and
code for synchronizing the evaluation result from the mirror cache file to the central cache file in response to a determination that the central cache file fails to include the evaluation result.
7. The non-transitory computer-readable medium of claim 6 further comprising code for synchronizing the evaluation result from the central cache file to the mirror cache file in response to a determination that the mirror cache file fails to include the evaluation result.
8. The non-transitory computer-readable medium of claim 6 further comprising code for delaying instantiation of the parameterized cell from an evaluation stage to an instance header binding stage.
9. The non-transitory computer-readable medium of claim 6 further comprising code for receiving the evaluation results associated with the parameterized cell in the design from one or more parameterized cell evaluators.
10. The non-transitory computer-readable medium of claim 6 further comprising:
code for receiving information associated with the parameterized cell;
code for performing one or more evaluations to determine the variant; and
code for generating information associated with the variant.
11. A system for placing option devices within circuits, the system comprising:
a processor; and
a memory configured to store a set of instructions that when executed by the processor configure the processor to:
persist evaluation results associated with a variant of a parameterized cell at a location in at least one of a central cache file or a mirror cache file in a design library;
map the variant to the location;
instantiate the parameterized cell from either the cache file or the mirrored cache file when the cache file or the mirrored cache file contains the evaluation result; and
synchronize the evaluation result from the mirror cache file to the central cache file in response to a determination that the central cache file fails to include the evaluation result.
12. The system of claim 11 wherein the set of instructions further configure the processor to synchronize the evaluation result from the central cache file to the mirror cache file in response to a determination that the mirror cache file fails to include the evaluation result.
13. The system of claim 11 wherein the set of instructions further configure the processor to delay instantiation of the parameterized cell from an evaluation stage to an instance header binding stage.
14. The system of claim 11 wherein the set of instructions further configure the processor to receive the evaluation results associated with the parameterized cell in the design from one or more parameterized cell evaluators.
15. The system of claim 11 wherein the set of instructions further configure the processor to:
receive information associated with the parameterized cell;
perform one or more evaluations to determine the variant; and
generate information associated with the variant.