IP Library Granted Patent US 9,563,090
Granted Patent B2
US 9,563,090 · App. 14/543,363 · Granted Feb 7, 2017

Liquid crystal panel, liquid crystal display device, and manufacturing method thereof

Inventor: Kikuo Ono (Chiba, JP)
Assignee: Panasonic Liquid Crystal Display Co., Ltd.
G02F1/134363G02F1/1362G02F1/1368G02F1/136227G02F1/136286G02F1/13439G02F1/13458G02F2001/13629G02F2001/134372G02F2001/136231G02F2001/136236G02F2001/136295H01L27/1288H01L29/41733
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Quick Facts
Patent No.
US 9,563,090
App. No.
14/543,363
Granted
Feb 7, 2017
Kind
B2
Abstract

A gate line ( 40 ) has a two-layered structure comprising a lower gate line ( 40 a ) made of material identical to a pixel electrode ( 70 ), and positioned in the same layer as the pixel electrode ( 70 ), and an upper gate line ( 40 b ) layered on the lower gate line ( 40 b ), and made of material having a higher electrical conductivity than the transparent conductive material. According to this structure, it is possible to reduce the number of times performing exposure processes in manufacturing an in-plane switching type liquid crystal panel.

Claims (33)

1. A liquid crystal panel comprising:

first and second substrates sandwiching a liquid crystal material,

a thin film transistor formed on the first substrate,

a pixel electrode formed on the first substrate and made of a transparent conductive material,

a common electrode formed on the first substrate and made of a transparent conductive material,

a gate line connected to the thin film transistor and having a layer made of material identical to the pixel electrode and positioned in a same layer as the pixel electrode,

a first insulating layer covering the gate line and the pixel electrode,

a second insulating layer covering the first insulating layer,

a first contact hole penetrating to both the first insulating layer and the second insulating layer, and

a drain line connected to the thin film transistor and formed on the first insulating layer, wherein

the thin transistor film includes a source electrode formed on the first insulating layer,

the common electrode is formed on the second insulating layer,

the pixel electrode is electrically connected to a source electrode of the thin film transistor through the first contact hole via a connecting conductor,

a common line is formed in parallel with the drain line and is electrically connected to the common electrode through a second contact hole formed in the second insulating layer, and

the common line is formed in a same layer as the drain line.

2. The liquid crystal panel according to claim 1 , wherein the gate line has two-layered structure that comprises a lower line made of the same material as the pixel electrode and positioned in a common layer with the pixel electrode, and an upper line layered on the lower line and made of material having a higher electrical conductivity than the transparent conductive material.

3. The liquid crystal panel according to claim 1 , wherein the source electrode overlaps the pixel electrode in a plan view.

4. The liquid crystal panel according to claim 1 , wherein an end part of the source electrode is exposed from the second insulator and is connected to the connecting conductor.

5. The liquid crystal panel according to claim 1 , wherein the connecting conductor is made of the same material as the common electrode and is positioned in a common layer with the common electrode.

6. The liquid crystal panel according to claim 1 , wherein the common line is formed between the first insulating layer and the second insulating layer.

7. A liquid crystal panel comprising:

first and second substrates sandwiching a liquid crystal material,

a thin film transistor formed on the first substrate, a pixel electrode formed on the first substrate and made of a transparent conductive material,

a common electrode formed on the first substrate and made of a transparent conductive material,

a gate line connected to the thin film transistor and having a layer made of material identical to the pixel electrode and positioned in a layer same as the pixel electrode,

a first insulating layer covering the gate line and the pixel electrode, a second insulating layer covering the first insulating layer,

a first contact hole penetrating to both the first insulating layer and the second insulating layer, and

a drain line connected to the thin film transistor and formed on the first insulating layer, wherein

the thin transistor film includes a source electrode formed on the first insulating layer,

the common electrode is formed on the second insulating film,

the pixel electrode is electrically connected to a source electrode of the thin film transistor through the first contact hole via a connecting conductor,

a common line is formed in parallel with the drain line and is electrically connected to the common electrode through a second contact hole formed in the second insulating layer, and

the common line is formed between the first insulating layer and the second insulating film.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2023
From: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
To: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Reel/Frame 064292/0775 →
Priority Claims (1)
JP 2010-266443 · Nov 30, 2010 · national
Continuity (2)
Continuation 13306416 · Nov 29, 2011
Related Publication 20150070619A1 · Mar 12, 2015