Decision feedback equalizer for highly spectrally efficient communications
One or more embodiments describe a decision feedback equalizer for highly spectrally efficient communications. A method may be performed in a decision feedback equalizer (DFE). The method may include initializing values of tap coefficients of the DFE based on values of tap coefficients of a partial response filter through which said transmitted symbols passed en route to said sequence estimation circuit. The method may include receiving estimates of transmitted symbols from a sequence estimation circuit, and receiving an error signal that is generated based on an estimated partial response signal output by the sequence estimation circuit. The method may include updating values of tap coefficients of the DFE based on the error signal and the estimates of transmitted symbols. The method may include generating one or more constraints that restrict the impact of the error signal on the updating of the values of the tap coefficients of the DFE.
1. A system comprising:
a filter circuit configured to output its tap coefficients to circuitry external to said filter circuit; and
a sequence estimation circuit operable to perform a sequence estimation process, wherein said tap coefficients of said filter circuit are an input to said sequence estimation process.
2. The system of claim 1 , wherein said filter circuit accepts, as input, symbol decisions generated by said sequence estimation circuit.
3. The system of claim 1 , wherein an output of said sequence estimation process is an estimate of phase error for a received signal input to said sequence estimation circuit.
4. The system of claim 3 , wherein said filter circuit accepts, as input, said estimate of said phase error.
5. The system of claim 4 , wherein said filter circuit is operable to adapt said tap coefficients based on said estimate of phase error.
6. The system of claim 1 , wherein said filter circuit accepts, as input, an output of a feed forward equalizer of said receiver.
7. The system of claim 1 , wherein said filter circuit accepts, as input, a partial response error signal.
8. The system of claim 7 , wherein said partial response error signal is generated from an output of said sequence estimation circuit.
9. The system of claim 1 , wherein said filter circuit is operable to generate soft decisions as to symbols output by said sequence estimation circuit.
10. The system of claim 1 , wherein said filter circuit is a decision feedback equalizer.
11. A method comprising:
outputting, by a filter circuit of a receiver, tap coefficients to circuitry external to said filter circuit; and
performing, by a sequence estimation circuit of said receiver, a sequence estimation process, wherein said tap coefficients of said filter circuit are an input to said sequence estimation process.
12. The method of claim 11 , comprising accepting by said filter circuit, as input, symbol decisions generated by said sequence estimation circuit.
13. The method of claim 11 , comprising:
generating, by said sequence estimation circuit, an estimate of phase error for a received signal input to said sequence estimation circuit.
14. The method of claim 13 , comprising accepting by said filter circuit, as input, said estimate of said phase error.
15. The method of claim 14 , comprising adapting, by said filter circuit, said tap coefficients based on said estimate of phase error.
16. The method of claim 11 , comprising accepting by filter circuit, as input, an output of a feed forward equalizer of said receiver.
17. The method of claim 11 , comprising accepting by said filter circuit, as input, a partial response error signal.
18. The method of claim 17 , wherein said partial response error signal is generated from an output of said sequence estimation circuit.
19. The method of claim 11 , comprising generating, by said filter circuit, soft decisions as to symbols output by said sequence estimation circuit.
20. The method of claim 11 , wherein said filter circuit is a decision feedback equalizer.