System and method for synchronizing local oscillators
Provided is a method and apparatus for aligning a first local oscillator (LO) clock generated by a controllable LO clock generator in a first radio frequency (RF) path with a second LO clock in a second RF path. The apparatus includes a synchronization channel configured to exchange a synchronization clock between the first and second RF paths, a phase detector configured to measure a phase alignment between the first and second LO clocks, and a loop filter configured to drive the controllable LO clock generators using the phase alignment. Also provided is a time to digital converter. The time to digital converter includes a D flip-flop for sampling first and second input clocks with a third clock, and a counter configured to synchronously increment the resulting samples and create a digital proportional value representing the delay between the first and second clocks.
1. A time to digital converter comprising:
a D flip-flop for sampling first and second input clocks with a third clock; and
a counter configured to synchronously increment the resulting samples and create a digital proportional value representing the delay between the first and second clocks.
2. The time to digital converter of claim 1 , further comprising:
a set-reset latch for receiving the first and second input clocks;
wherein the first and second input clocks are trigger and target clocks as edge-triggered set and reset inputs to the set-reset latch; and
wherein the set-reset latch output is sampled with the third clock.
3. The time to digital converter of claim 1 , further comprising:
a decoder to detect sampled inputs where the first clock leads the second clock.
4. The time to digital converter of claim 1 , wherein a frequency of the third clock is selected to ensure that clock edges of the third clock process through a period of the first and second clocks, such that phase detector resolution is optimized.
5. The time to digital converter of claim 1 , wherein a number of cycles to count the sampled clocks is selected such that phase detector resolution is optimized.
6. The time to digital converter of claim 1 , wherein a phase discontinuity of the time to digital converter is detected to determine a lock point and prevent a false lock.
7. A method of time to digital conversion, comprising:
sampling first and second input clocks with a third clock;
using the resulting samples to synchronously increment a counter; and
creating a digital proportional value representing the delay between the first and second clocks.
8. The method of claim 7 , further comprising:
using trigger and target clocks as edge-triggered set and reset inputs to a set-reset latch; and
sampling the latch output with the third clock.
9. The method of claim 7 , further comprising:
detecting sampled inputs with a decoder where the first clock leads the second clock.
10. The method of claim 7 , further comprising:
determining a frequency of the third clock to ensure that clock edges of the third clock process through a period of the first and second clocks, such that phase detector resolution is optimized.
11. The method of claim 7 , further comprising:
determining a number of cycles to count the sampled clocks such that phase detector resolution is optimized.
12. The method of claim 7 , further comprising:
detecting a phase discontinuity to determine a lock point and prevent a false lock.