Integrated processor and CDR circuit
View Patent ↗A system may include a clock and data recovery circuit that includes one or more analog components. The system may also include a digital control circuit configured to control the clock and data recovery circuit. The digital control circuit and the clock and data recovery circuit may be formed on a single substrate.
1. A system, comprising:
a clock and data recovery circuit comprising one or more analog components configured to recover clock and data in an analog domain, the clock and data recovery circuit including one or more bipolar junction transistors, wherein the one or more bipolar junction transistors and other physical transistor level components of the analog components are formed in a substrate; and
a digital control circuit configured to receive data from the clock and data recovery circuit, determine a performance of the clock and data recovery circuit based on the data, and adjust settings within the clock and data recovery circuit to reduce power consumption of the clock and data recovery circuit while the performance of the clock and data recovery circuit is maintained above a threshold level achieved before the settings are adjusted, the digital control circuit further configured to control the clock and data recovery circuit, the digital control circuit further configured to control the clock and data recovery circuit in a digital domain, the digital control circuit including one or more complementary metal-oxide semiconductor transistors, wherein the one or more complementary metal-oxide semiconductor transistors and other physical transistor level components of the digital control circuit are formed in the substrate, wherein the digital control circuit is further configured to alter locking dynamics of the clock and data recovery circuit by adjusting one or more of the following:
a gain of a charge pump within the clock and data recovery circuit,
voltage rail levels of the charge pump,
an initial starting frequency of a voltage controlled oscillator within the clock and data recovery circuit, and
a frequency step size of the voltage controlled oscillator, and
wherein the one or more bipolar junction transistors of the clock and data recovery circuit communicate on the substrate with the one or more complementary metal-oxide semiconductor transistors of the digital control circuit.
2. The system of claim 1 , further comprising a memory unit coupled to the digital control circuit, the digital control circuit configured to store data regarding the clock and data recovery circuit within the memory unit, the data including one or more of: a voltage level of the clock and data recovery circuit, power consumption of the clock and data recovery circuit, a data rate of a data signal received by the clock and data recovery circuit, a temperature of the clock and data recovery circuit, and transmit and receive power levels of the clock and data recovery circuit.
3. The system of claim 1 , wherein the one or more analog components of the clock and data recovery circuit includes a clock generating circuit and a conditioning circuit coupled to the clock generating circuit, wherein the conditioning circuit conditions a data signal before sending the data signal to the clock generating circuit and the clock generating circuit extracts a clock signal from the data signal.
4. The system of claim 1 , further comprising:
a second clock and data recovery circuit comprising one or more analog components formed on the substrate;
a third clock and data recovery circuit comprising one or more analog components formed on the substrate; and
a fourth clock and data recovery circuit comprising one or more analog components formed on the substrate, wherein the digital control circuit is configured to control each of the second, third, and fourth clock and data recovery circuits.
5. A system, comprising:
a clock and data recovery circuit comprising one or more analog components configured to recover clock and data in an analog domain, the clock and data recovery circuit including one or more bipolar junction transistors that are formed in a substrate; and
a digital control circuit configured to receive data from the clock and data recovery circuit, determine a performance of the clock and data recovery circuit based on the data, and adjust settings within the clock and data recovery circuit to reduce power consumption of the clock and data recovery circuit while the performance of the clock and data recovery circuit is maintained above a threshold level achieved before the settings are adjusted, the digital control circuit further configured to control the clock and data recovery circuit, the digital control circuit further configured to control the clock and data recovery circuit in a digital domain, the digital control circuit including one or more complementary metal-oxide semiconductor transistors that are formed in the substrate, wherein the digital control circuit is further configured to alter locking dynamics of the clock and data recovery circuit, by adjusting one or more of the following:
a gain of a charge pump within the clock and data recovery circuit,
voltage rail levels of the charge pump,
an initial starting frequency of a voltage controlled oscillator within the clock and data recovery circuit, and
a frequency step size of the voltage controlled oscillator, and
wherein the one or more bipolar junction transistors of the clock and data recovery circuit communicate on the substrate with the one or more complementary metal-oxide semiconductor transistors of the digital control circuit.
6. The system of claim 5 , wherein the clock and data recovery circuit includes:
a first phase detector configured to generate a first signal based on a comparison of an input signal and a oscillator signal;
a second phase detector configured to generate a second signal based on a comparison of the input signal and the oscillator signal; and
an oscillator configured to generate the oscillator signal based on the first signal when the clock and data recovery circuit is locking to the input signal and to generate the oscillator signal based on the second signal when the clock and data recovery circuit is locked to the input signal.
7. The system of claim 6 , wherein the second phase detector is an Alexander phase detector.
8. The system of claim 6 , wherein the clock and data recovery circuit further includes a driver circuit configured to drive a clock signal out of the clock and data recovery circuit, wherein the clock signal driven by the driver circuit is based on an output of the second phase detector and is phase aligned with the input signal.
9. The system of claim 6 , wherein the clock and data recovery circuit further includes a charge pump coupled to the first and second phase detectors, the charge pump configured to generate an control signal based on either the first signal or the second signal, wherein the oscillator signal is based on the control signal, wherein the digital control circuit selects which of the first signal and the second signal is provided to the charge pump based on a bit error rate of the input signal calculated with the oscillator signal being above a threshold.
10. The system of claim 9 , wherein the digital control circuit is configured to set rail voltages of the charge pump at a first set of voltages when the clock and data recovery circuit is locking to the input signal and to set the rail voltages of the charge pump at a second set of voltages after the clock and data recovery circuit locks to the input signal, wherein a first difference between voltages of the first set of voltages is smaller than a second difference between voltages of the second set of voltages.