IP Library Granted Patent US 9,842,877
Granted Patent B2
US 9,842,877 · App. 14/553,697 · Granted Dec 12, 2017

Semiconductor device and manufacturing method thereof

Inventor: Keiichi Itagaki (Kanagawa, JP)
Assignee: RENESAS ELECTRONICS CORPORATION
H01L27/1463H01L27/14612H01L27/14643H01L27/14687H01L27/14689H01L27/14627
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Quick Facts
Patent No.
US 9,842,877
App. No.
14/553,697
Granted
Dec 12, 2017
Kind
B2
Abstract

A semiconductor device includes a semiconductor substrate, a photoelectric conversion element, a first isolation insulating film, and a current blocking region. The first isolation insulating film is formed around the photoelectric conversion element. The current blocking region is formed in a region between the photoelectric conversion element and the first isolation insulating film. The current blocking region includes an impurity diffusion layer, and a defect extension preventing layer disposed in contact with the impurity diffusion layer to form a twin with the impurity diffusion layer. The defect extension preventing layer has a different crystal structure from that of the impurity diffusion layer. At least a part of the current blocking region is disposed in contact with the first isolation insulating film.

Claims (30)

1. A semiconductor device, comprising:

a semiconductor substrate having a main surface;

a photoelectric conversion element formed in the semiconductor substrate;

a first isolation insulating film formed around the photoelectric conversion element over the main surface;

a current blocking region formed in a region between the photoelectric conversion element and the first isolation insulating film over the main surface and in contact with the first isolation insulating film; and

an interlayer insulating film over the main surface so as to cover the photoelectric conversion element and the current blocking region,

wherein the current blocking region includes a defect extension preventing layer and an impurity diffusion layer,

wherein the defect extension preventing layer is at an upper part of the current blocking region in contact with the interlayer insulating film and is a region with a neutral polarity with at least one element selected from the group comprised of nitrogen, silicon, germanium, fluorine, and argon implanted therein,

wherein the impurity diffusion layer is at a lower part of the current blocking region and is a region with a p-type polarity with boron implanted therein,

wherein the defect extension preventing layer has a different crystal structure from the impurity diffusion layer, and

wherein the impurity diffusion layer and the defect extension preventing layer are in contact with each other so as to form a twin.

2. The semiconductor device according to claim 1 ,

wherein the first isolation insulating film is a LOCOS oxide film that has a shape expanding toward an upper side and a lower side of the main surface.

3. The semiconductor device according to claim 1 ,

wherein the first isolation insulating film is an STI oxide film made of an insulating film that fills a trench formed from the main surface in the semiconductor substrate.

4. The semiconductor device according to claim 1 ,

wherein the defect extension preventing layer is formed from the main surface to a region in a depth of 40 nm or more in a direction vertical to the main surface.

5. The semiconductor device according to claim 1 ,

wherein a diffusion region for isolation is disposed in contact with a bottom surface of the first isolation insulating film.

6. The semiconductor device according to claim 1 ,

wherein the main surface includes a pixel region and a peripheral circuit region,

wherein the photoelectric conversion element, the current blocking region, and the first isolation insulating film are formed in the pixel region,

wherein the semiconductor device further comprises:

a semiconductor element formed in the semiconductor substrate in the peripheral circuit region; and

a second isolation insulating film around the semiconductor element over the main surface in the peripheral circuit region, and

wherein the second isolation insulating film is formed more deeply than the first isolation insulating film.

7. The semiconductor device according to claim 6 ,

wherein each of the first and second isolation insulating films is a LOCOS that has a shape expanding toward an upper side and a lower side of the main surface.

8. The semiconductor device according to claim 6 ,

wherein each of the first and second isolation insulating films is an STI made of an insulating film that fills a trench formed from the main surface in the semiconductor substrate.

Assignments (2)
CHANGE OF ADDRESS OF ASSIGNEE Recorded Jun 1, 2018
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 045984/0759 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 25, 2014
From: ITAGAKI, KEIICHI
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 034265/0242 →
Priority Claims (1)
JP 2013-244817 · Nov 27, 2013 · national
Continuity (1)
Related Publication 20150145092A1 · May 28, 2015