IP Library Granted Patent US 9,287,298
Granted Patent B2
US 9,287,298 · App. 14/554,833 · Granted Mar 15, 2016

Liquid crystal display and manufacturing method thereof

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Quick Facts
Patent No.
US 9,287,298
App. No.
14/554,833
Granted
Mar 15, 2016
Kind
B2
Abstract

A liquid crystal display includes: a first substrate, a gate line and a data line disposed on the first substrate, a thin film transistor connected to the gate line and the data line, a first passivation layer disposed on the thin film transistor, a first electrode disposed on the first passivation layer, a second passivation layer disposed on the first electrode and a second electrode disposed on the second passivation layer. A first edge of the first electrode and a second edge of the second passivation layer have substantially the same plane shape as each other, and the second edge of the second passivation layer protrudes more than the first edge of the first electrode.

Claims (96)

1. A liquid crystal display comprising:

a first substrate;

a gate line and a data line disposed on the first substrate;

a thin film transistor connected to the gate line and the data line;

a first passivation layer disposed on the thin film transistor;

a first electrode disposed on the first passivation layer;

a second passivation layer disposed on the first electrode; and

a second electrode disposed on the second passivation layer,

wherein a first edge of the first electrode and a second edge of the second passivation layer have substantially a same plane shape as each other, and the second edge of the second passivation layer protrudes more than the first edge of the first electrode.

2. The liquid crystal display of claim 1 , wherein the first passivation layer comprises a first drain contact hole exposing a drain electrode of the thin film transistor, the first electrode comprises a second drain contact hole exposing the drain electrode, the second passivation layer comprises a third drain contact hole exposing the drain electrode,

the first drain contact hole, the second drain contact hole, and the third drain contact hole overlap with each other, and

a size of the second drain contact hole is greater than a size of the third drain contact hole.

3. The liquid crystal display of claim 2 , further comprising an organic layer disposed between the first passivation layer and the first electrode,

the first drain contact hole is disposed in the first passivation layer and the organic layer, and

an edge of the second drain contact hole and an edge of the third drain contact hole overlap with an inclined portion that forms the first drain contact hole of the organic layer.

4. The liquid crystal display of claim 3 , wherein the second electrode is connected with the drain electrode through the first drain contact hole, the second drain contact hole, and the third drain contact hole, and

a thickness of the second electrode is greater than a thickness of the first electrode.

5. The liquid crystal display of claim 4 , wherein the thickness of the second electrode is about two times thicker than the thickness of the first electrode.

6. The liquid crystal display of claim 2 , wherein the second electrode is connected with the drain electrode through the first drain contact hole, the second drain contact hole, and the third drain contact hole, and

a thickness of the second electrode is greater than a thickness of the first electrode.

7. The liquid crystal display of claim 6 , wherein the thickness of the second electrode is about two times thicker than the thickness of the first electrode.

8. The liquid crystal display of claim 1 , further comprising a gate signal transmission pad portion disposed on a same layer as the data line,

wherein the gate line comprises a gate pad portion,

the first passivation layer comprises a first pad contact hole exposing the gate pad portion and a second pad contact hole exposing the gate signal transmission pad portion,

a connection member disposed on the first pad contact hole and the second pad contact hole,

an insulation portion disposed on the same layer as the second passivation layer and is disposed on the connecting member, and

wherein an edge of the insulation portion protrudes more than an edge of the connection member.

9. The liquid crystal display of claim 1 , wherein the data line comprises a data pad portion,

the first passivation layer comprises a third pad contact hole exposing the data pad portion,

a contact auxiliary member is disposed on the third pad contact hole, and

the second passivation layer does not overlap with the data pad portion.

10. A liquid crystal display comprising:

a first substrate;

a gate line and a data line disposed on the first substrate;

a thin film transistor connected to the gate line and the data line;

a first passivation layer disposed on the thin film transistor;

a first electrode disposed on the first passivation layer;

a second passivation layer disposed on the first electrode; and

a second electrode disposed on the second passivation layer,

wherein the first passivation layer comprises a first drain contact hole exposing a drain electrode of the thin film transistor, the first electrode comprises a second drain contact hole exposing the drain electrode, and the second passivation layer comprises a third drain contact hole exposing the drain electrode,

the first drain contact hole, the second drain contact hole, and the third drain contact hole overlap with each other, and

a size of the second drain contact hole is greater than a size of the third drain contact hole.

11. The liquid crystal display of claim 10 , further comprising an organic layer disposed between the first passivation layer and the first electrode,

wherein the first drain contact hole is disposed in the first passivation layer and the organic layer, and

an edge of the second drain contact hole and an edge of the third drain contact hole overlap with an inclined portion that forms the first drain contact hole of the organic layer.

12. The liquid crystal display of claim 10 , wherein the second electrode is connected with the drain electrode through the first drain contact hole, the second drain contact hole, and the third drain contact hole, and

a thickness of the second electrode is greater than a thickness of the first electrode.

13. The liquid crystal display of claim 12 , wherein the thickness of the second electrode is about two times thicker than the thickness of the first electrode.

14. The liquid crystal display of claim 10 , wherein the second electrode is connected with the drain electrode through the first drain contact hole, the second drain contact hole, and the third drain contact hole, and

a thickness of the second electrode is greater than a thickness of the first electrode.

15. The liquid crystal display of claim 14 , wherein the thickness of the second electrode is about two times thicker than the thickness of the first electrode.

16. The liquid crystal display of claim 10 , further comprising a gate signal transmission pad portion disposed on the same layer as the data line,

wherein the gate line comprises a gate pad portion,

the first passivation layer comprises a first pad contact hole exposing the gate pad portion and a second pad contact hole exposing the gate signal transmission pad portion,

a connection member is disposed on the first pad contact hole and the second pad contact hole,

an insulation portion is disposed on the same layer as the second passivation layer and is disposed on the connecting member, and

wherein an edge of the insulation portion protrudes more than an edge of the connection member.

17. The liquid crystal display of claim 10 , wherein the data line comprises a data pad portion,

the first passivation layer comprises a third pad contact hole exposing the data pad portion,

a contact auxiliary member is disposed on the third pad contact hole, and

the second passivation layer does not overlap with the data pad portion.

18. A method for manufacturing a liquid crystal display, comprising:

forming a gate line, a data line, and a thin film transistor connected to the gate line and the data line on a first substrate;

forming a first passivation layer including a first drain contact hole that exposes a drain electrode of the thin film transistor on the thin film transistor;

forming a first electrode including a second drain contact hole exposing the drain electrode and a second passivation layer including a third drain contact hole exposing the drain electrode together on the first passivation layer through one photolithography process;

forming a second electrode on the second passivation layer;

forming the first drain contact hole, the second drain contact hole, and the third drain contact hole to be overlapped with each other; and

forming a size of the second drain contact hole to be greater than a size of the third drain contact hole.

19. The method for manufacturing the liquid crystal display of claim 18 , wherein the forming of the first electrode and the second passivation layer together comprises:

depositing a first layer on the first passivation layer;

depositing a second layer on the first layer;

forming a photosensitive film pattern on the second layer;

etching the second layer using the photosensitive film pattern as a mask; and

over-etching the first layer using the photosensitive film pattern as a mask.

20. The method for manufacturing the liquid crystal display of claim 19 , further comprising forming an organic layer between the first passivation layer and the first electrode,

wherein the first drain contact hole is formed in the first passivation layer and the organic layer,

the organic layer includes an inclined portion at a peripheral area of the first drain contact hole, and

an edge of the second drain contact hole and an edge of the third drain contact hole are formed to be overlapped with the inclined portion of the organic layer.

21. The method for manufacturing the liquid crystal display of claim 20 , wherein

the second electrode is formed to be connected with the drain electrode through the first drain contact hole, the second drain contact hole, and the third drain contact hole, and

a thickness of the second electrode is greater than a thickness of the first electrode.

22. The method for manufacturing the liquid crystal display of claim 21 , wherein a thickness of the second electrode is about two times thicker than a thickness of the first electrode.

23. The method for manufacturing the liquid crystal display of claim 18 , wherein the second electrode is formed to be connected with the drain electrode through the first drain contact hole, the second drain contact hole, and the third drain contact hole, and

a thickness of the second electrode is greater than a thickness of the first electrode.

24. The method for manufacturing the liquid crystal display of claim 23 , wherein the thickness of the second electrode is about two times thicker than the thickness of the first electrode.

25. The method for manufacturing the liquid crystal display of claim 18 , wherein the gate line comprises a gate pad portion,

the forming of the first passivation layer further comprises forming a first pad contact hole exposing the gate pad portion, and

the forming of the first electrode and the second passivation layer further comprises

forming a connection member on the first pad contact hole and

forming an insulation portion formed of the same layer as the second passivation layer on the connecting member, and

wherein an edge of the insulating layer is protruded more than an edge of the connection member.

26. The method for manufacturing the liquid crystal display of claim 18 , wherein

the data line comprises a data pad portion,

the forming of the first passivation layer further comprises forming a third pad contact hole exposing the data pad portion,

the forming of the second electrode further comprises forming a contact auxiliary member on the third pad contact hole, and

the second passivation layer is formed to not be overlapped with the data pad portion.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2026
From: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
To: LONESTAR CRYSTAL DISPLAY LLC
Reel/Frame 074944/0730 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 21, 2022
From: SAMSUNG DISPLAY CO., LTD.
To: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
Reel/Frame 060778/0543 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 26, 2014
From: CHOI, JAE HO; PARK, JAE-HYUN
To: SAMSUNG DISPLAY CO., LTD
Reel/Frame 034271/0302 →