Transport network
View Patent ↗Some embodiments provide a method of monitoring the implementation of a user design in a configurable integrated circuit (IC). The method receives a user design for an IC and optimizes the user design to produce a second IC design. The optimization results in the elimination of circuit element(s). The method defines the second IC design for the configurable IC and generates output data for the eliminated circuit element(s) to allow for monitoring the user design.
1. A method for monitoring a programmable integrated circuit (IC), the method comprising:
with a debug system, monitoring a plurality of data bits from a plurality of configurable circuits configurably performing a plurality of operations in the programmable IC; and
with a subset of the plurality of configurable circuits, providing the monitored plurality of data bits to a transport network in the programmable IC, wherein the transport network operates a plurality of slots, each slot for transporting one data bit to a set of destination circuits, wherein each data bit of the monitored plurality of data bits is provided to the transport network by delaying each data bit from entering the transport network until a slot becomes available for transporting that monitored data bit, wherein the plurality of configurable circuits are implemented on the programmable IC.
2. The method of claim 1 , wherein the transport network comprises a plurality of stages and the plurality of configurable circuits are arranged in a plurality of groups of configurable circuits, wherein each stage of the transport network receives monitored data bits from one respective group of configurable circuits.
3. The method of claim 1 , wherein monitoring the plurality of data bits comprises sampling the plurality of configurable circuits once every clock cycle.
4. The method of claim 3 , wherein each clock cycle is divided into a plurality of sub-cycles, wherein an available slot corresponds to a sub-cycle of the plurality of sub-cycles during which a section of the transport network is not transporting a data bit.
5. The method of claim 4 , wherein delaying a monitored data bit from entering the transport network comprises storing the delayed monitored data bit at a storage circuit until a given slot becomes available for transporting the delayed monitored data bit.
6. The method of claim 1 , further comprising:
with a trace buffer in the set of destination circuits, storing a portion of the monitored plurality of data bits.
7. The method of claim 6 , further comprising:
with a trigger circuit in the set of destination circuits, detecting that a predetermined condition has been met; and
with the trigger circuit in the set of destination circuits, instructing the trace buffer to stop receiving new data bits.
8. The method of claim 7 , further comprising:
with a deskew circuit in the set of destination circuits, temporally aligning the plurality of monitored data bits.
9. A method for monitoring a programmable integrated circuit (IC) comprising:
with a configuration network, configuring a first set of configurable circuits to monitor a plurality of data bits from a plurality of configurable circuits configurably performing a plurality of operations in the programmable IC; and
with the configuration network, configuring a second set of configurable circuits to provide the monitored plurality of data bits to a transport network that operates a plurality of slots, each slot for transporting one data bit to a set of destination circuits, wherein configuring the second set of configurable circuits to provide the monitored plurality of data bits to the transport network comprises configuring the second set of configurable circuits to delay each monitored data bit from entering the transport network until a slot becomes available for transporting that monitored data bit, wherein the first and second sets of configurable circuits are implemented on the programmable IC.
10. The method of claim 9 , wherein the transport network comprises a plurality of stages and the plurality of configurable circuits are arranged in a plurality of groups of configurable circuits, wherein each stage of the transport network receives monitored data bits from one respective group of configurable circuits.
11. The method of claim 9 , wherein configuring the first set of configurable circuits to monitor the plurality of data bits comprises configuring the first set of configurable circuits to sample the plurality of configurable circuits once every clock cycle.
12. The method of claim 11 , wherein each clock cycle is divided into a plurality of sub-cycles, wherein an available slot corresponds to a sub-cycle of the plurality of sub-cycles during which a section of the transport network is not transporting a data bit.
13. The method of claim 12 , wherein configuring the set of configurable circuits to delay a monitored data bit from entering the transport network comprises configuring the second set of configurable circuits to store the delayed monitored data bit at a storage circuit until a given slot becomes available for transporting the delayed monitored data bit.
14. The method of claim 9 , further comprising:
with a trace buffer in the set of destination circuits, storing a portion of the monitored plurality of data bits.
15. The method of claim 14 , further comprising:
with a trigger circuit in the set of destination circuits, detecting that a predetermined condition has been met; and
with the trigger circuit in the set of destination circuits, instructing the trace buffer to stop receiving new data bits.
16. The method of claim 15 , further comprising:
with a deskew circuit in the set of destination circuits, temporally aligning the plurality of monitored data bits.