In-memory computational device
A computing device comprising includes a memory array having a plurality of sections with memory cells arranged in rows and column, at least one cell in each column of the memory array connected to a bit line having a bit line voltage associated with a logical 1 or a logical 0. The computing device additionally includes at least one multiplexer to connect a bit line in a column of a first section to a bit line in a column in a second section different from the first section and a decoder to activate a word line connected to a cell in the column in the second section to write the bit line voltage into the cell.
1. A computing device comprising:
a memory array comprising a plurality of sections having memory cells arranged in rows and column, at least one cell in each column of said memory array connected to a bit line having a bit line voltage associated with a logical 1 or a logical 0; and
at least one multiplexer to connect a bit line in a column of a first section to a bit line in a column in a second section different from said first section; and
a decoder to activate a word line connected to a cell in said column in said second section to write said bit line voltage into said cell; and
a controller to provide said decoder with an instruction set for decoding in said decoder wherein said instruction set represents compressed data associated with the operation of any one of said memory array, said at least one multiplexer, and said decoder.
2. A computing device according to claim 1 wherein said decoder decompresses said compressed data.
3. A computing device comprising:
a memory array comprising a plurality of sections having memory cells arranged in rows and column, at least one cell in each column of said memory array connected to a bit line having a bit line voltage associated with a logical 1 or a logical 0; and
at least one multiplexer to connect a bit line in a column of a first section to a bit line in a column in a second section different from said first section; and
a decoder to activate a word line connected to a cell in said column in said second section to write said bit line voltage into said cell and to simultaneously access a plurality of read word lines and write word lines in said memory array.
4. A computing device comprising:
a memory array comprising a plurality of sections having memory cells arranged in rows and column, at least one cell in each column of said memory array connected to a bit line having a bit line voltage associated with a logical 1 or a logical 0; and
at least one multiplexer to connect a bit line in a column of a first section to a bit line in a column in a second section different from said first section; and
a decoder to activate a word line connected to a cell in said column in said second section to write said bit line voltage into said cell; and
a controller to provide said decoder with an instruction set for decoding in said decoder wherein said decoder decodes said instruction set from said controller into an instruction set for accessing in parallel a plurality of read word lines and write word lines in said memory array.
5. A computing device comprising:
a memory array comprising a plurality of sections having memory cells arranged in rows and column, at least one cell in each column of said memory array connected to a bit line having a bit line voltage associated with a logical 1 or a logical 0; and
at least one multiplexer to connect a bit line in a column of a first section to a bit line in a column in a second section different from said first section; and
a decoder to activate a word line connected to a cell in said column in said second section to write said bit line voltage into said cell wherein said decoder comprises a memory array comprising a plurality of memory cells arranged in rows and columns, at least one cell in each column being connected to a bit line having a bit line voltage associated with a logical 1 or a logical 0 wherein activation of said word line is through said bit line in said decoder.
6. A computing device comprising:
a memory array comprising a plurality of sections having memory cells arranged in rows and column, at least one cell in each column of said memory array connected to a bit line having a bit line voltage associated with a logical 1 or a logical 0; and
at least one multiplexer to connect a bit line in a column of a first section to a bit line in a column in a second section different from said first section; and
a decoder to activate a word line connected to a cell in said column in said second section to write said bit line voltage into said cell wherein said decoder comprises a memory array comprising a plurality of memory cells arranged in rows and columns with only one memory cell in each column and wherein said memory cell is connected to a bit line having a bit line voltage associated with a logical 1 or a logical 0.
7. A method of performing in-memory computations in a memory array comprising a plurality of sections having memory cells arranged in rows and column, at least one cell in each column of said memory array connected to a bit line having a bit line voltage associated with a logical 1 or a logical 0, the method comprising:
connecting a bit line in a column of a first section to a bit line in a column in a second section different from said first section;
activating a word line connected to a cell in said column in said second section; and writing said bit line voltage into said cell; and
decompressing compressed data represented by a small size instruction set into a large size instruction set.
8. A method of performing in-memory computations in a memory array comprising a plurality of sections having memory cells arranged in rows and column, at least one cell in each column of said memory array connected to a bit line having a bit line voltage associated with a logical 1 or a logical 0, the method comprising:
connecting a bit line in a column of a first section to a bit line in a column in a second section different from said first section;
activating a word line connected to a cell in said column in said second section; and writing said bit line voltage into said cell; and
comprising simultaneously accessing a plurality of read word lines and write word lines.
9. A method of performing in-memory computations in a memory array comprising a plurality of sections having memory cells arranged in rows and column, at least one cell in each column of said memory array connected to a bit line having a bit line voltage associated with a logical 1 or a logical 0, the method comprising:
connecting a bit line in a column of a first section to a bit line in a column in a second section different from said first section;
activating a word line connected to a cell in said column in said second section; and writing said bit line voltage into said cell; and
activating said word line with a bit line voltage.