Noise shielding techniques for ultra low current measurements in biochemical applications
A device having an integrated noise shield is disclosed. The device includes a plurality of vertical shielding structures substantially surrounding a semiconductor device. The device further includes an opening above the semiconductor device substantially filled with a conductive fluid, wherein the plurality of vertical shielding structures and the conductive fluid shield the semiconductor device from ambient radiation. In some embodiments, the device further includes a conductive bottom shield below the semiconductor device shielding the semiconductor device from ambient radiation. In some embodiments, the opening is configured to allow a biological sample to be introduced into the semiconductor device. In some embodiments, the vertical shielding structures comprise a plurality of vias, wherein each of the plurality of vias connects more than one conductive layers together. In some embodiments, the device comprises a nanopore device, and wherein the nanopore device comprises a single cell of a nanopore array.
1. A device having an integrated well, comprising:
a plurality of vertical structures substantially surrounding a semiconductor device;
an opening above the semiconductor device substantially filled with a conductive fluid;
more than one conductive layers forming a portion of the integrated well; and
an oxide layer between the more than one conductive layers, and wherein the oxide layer is configured to form a capacitor.
2. The device of claim 1 , wherein the more than one conductive layers comprise a conductive bottom layer below the semiconductor device.
3. The device of claim 1 , wherein the more than one conductive layers comprises a metal layer.
4. The device of claim 1 , wherein the more than one conductive layers comprises a substrate layer.
5. The device of claim 1 , wherein the opening is configured to allow a biological sample to be introduced into the semiconductor device.
6. The device of claim 1 , wherein the vertical structures comprise a plurality of vias, wherein each of the plurality of vias connects more than one conductive layers together.
7. The device of claim 6 , wherein the plurality of vias are arranged in a single concentric ring surrounding the semiconductor device.
8. The device of claim 6 , wherein the plurality of vias are arranged in a plurality of concentric rings, and wherein the vias in a first ring of vias are offset from the vias in a second ring of vias.
9. The device of claim 1 , wherein the conductive fluid comprises an electrolyte.
10. The device of claim 1 , wherein the device comprises a nanopore device, and wherein the nanopore device comprises a single cell of a nanopore array.
11. The device of claim 1 , further comprising a conductive layer forming a portion of the integrated well, wherein the conductive layer is above the plurality of vertical structures, and wherein the conductive layer is extended horizontally and radially outwards from the plurality of vertical structures.
12. A device having an integrated well, comprising:
a plurality of vertical structures substantially surrounding a semiconductor device;
an opening above the semiconductor device substantially filled with a conductive fluid;
an oxide layer insulating a conductive layer from the conductive fluid, wherein the oxide layer is configured to form a capacitor.
13. A method for forming an integrated well for a semiconductor device, comprising:
providing a plurality of vertical structures substantially surrounding a semiconductor device; and
providing an opening above the semiconductor device substantially filled with a conductive fluid;
providing more than one conductive layers to form a portion of the integrated well; and
providing an oxide layer between the more than one conductive layers, and wherein the oxide layer is configured to form a capacitor.
14. The method of claim 13 , wherein the more than one conductive layers comprise a conductive bottom layer below the semiconductor device.
15. The method of claim 13 , wherein the opening is configured to allow a biological sample to be introduced into the semiconductor device.
16. The method of claim 13 , wherein the vertical structures comprise a plurality of vias, wherein each of the plurality of vias connects more than one conductive layers together.
17. The method of claim 16 , wherein the plurality of vias are arranged in a single concentric ring surrounding the semiconductor device.
18. The method of claim 16 , wherein the plurality of vias are arranged in a plurality of concentric rings, and wherein the vias in a first ring of vias are offset from the vias in a second ring of vias.
19. The method of claim 13 , wherein the conductive fluid comprises an electrolyte.
20. The method of claim 13 , wherein the device comprises a nanopore device, and wherein the nanopore device comprises a single cell of a nanopore array.