Electronic device and method for fabricating the same

1. An electronic device comprising a semiconductor memory unit that includes:

a first structure including a first magnetic layer, a second magnetic layer, a tunnel barrier layer which is interposed between the first magnetic layer and the second magnetic layer and a magnetic insulation layer provided over the second magnetic layer; and

a second structure disposed over the first structure, and including a magnetic correction layer for correcting a magnetic field of the first structure,

wherein a width of a bottom surface of the second structure is larger than a width of a top surface of the first structure directly contacted to the bottom surface of the second structure,

wherein the width of the bottom surface of the second structure is larger than a width of a top surface of the magnetic insulation layer directly contacted to the bottom surface of the second structure.

2. The electronic device according to claim 1 , wherein the first structure has a width that gradually increases in a downward direction.

3. The electronic device according to claim 2 , wherein sidewalls of the second structure have a profile that is vertical.

4. The electronic device according to claim 1 , wherein the second structure further includes a conductive top layer provided over the magnetic correction layer.

5. The electronic device according to claim 1 ,

wherein the first magnetic layer has a magnetization direction that is substantially vertical with respect to a surface of the first magnetic layer and is changeable,

wherein the second magnetic layer has a magnetization direction that is substantially vertical with respect to a surface of the second magnetic layer and is pinned, and

wherein the magnetic correction layer has a magnetization direction that is substantially opposite to the magnetization direction of the second magnetic layer.

6. The electronic device according to claim 5 , wherein a width of a bottom surface of the magnetic correction layer is W1, a width of the tunnel barrier layer is W2, and a width of a damaged portion of the magnetic correction layer is W3, and

wherein W3/2≤(W1−W2)/2≤W3.

7. The electronic device according to claim 1 , further comprising:

a contact disposed under the first structure and electrically coupled to the first structure,

wherein a width of a bottom surface of the first structure is equal to or smaller than a width of a top surface of the contact.

8. The electronic device according to claim 1 , further comprising a microprocessor which includes:

a control unit configured to receive a signal including a command from an outside of the microprocessor, and perform extracting, decoding of the command, or controlling input or output of a signal of the microprocessor;

an operation unit configured to perform an operation based on a result that the control unit decodes the command; and

a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed,

wherein the semiconductor memory unit is part of the memory unit in the microprocessor.

9. The electronic device according to claim 1 , further comprising a processor which includes:

a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data;

a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and

a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit,

wherein the semiconductor memory unit is part of the cache memory unit in the processor.

10. The electronic device according to claim 1 , further comprising a processing system which includes:

a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command;

an auxiliary memory device configured to store a program for decoding the command and the information;

a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and

an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside,

wherein the semiconductor memory unit is part of the auxiliary memory device or the main memory device in the processing system.

11. The electronic device according to claim 1 , further comprising a data storage system which includes:

a storage device configured to store data and conserve stored data regardless of power supply;

a controller configured to control input and output of data to and from the storage device according to a command inputted form an outside;

a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and

an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside,

wherein the semiconductor memory unit is part of the storage device or the temporary storage device in the data storage system.

12. The electronic device according to claim 1 , further comprising a memory system which includes:

a memory configured to store data and conserve stored data regardless of power supply;

a memory controller configured to control input and output of data to and from the memory according to a command inputted form an outside;

a buffer memory configured to buffer data exchanged between the memory and the outside; and

an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside,

wherein the semiconductor memory unit is part of the memory or the buffer memory in the memory system.