Flash memory module for realizing high reliability
View Patent ↗A flash memory module may include a plurality of flash memory chips. The memory chips may include one or more blocks. Each block may be a unit of erasing data. A flash controller may be coupled to the plurality of flash memory chips. The flash controller may program data to block and erase data from a block. The flash controller may manage a recent programming time for each of the plurality of blocks. The flash controller may erase data stored in a block for which an elapsed programming time is larger than a first value.
1. A flash memory module comprising:
a plurality of flash memory chips including a plurality of blocks, each of which is an unit of erasing data, and
a flash controller, which is coupled to the plurality of flash memory chips, configured to program data to a block and erase data from a block, wherein
the flash controller is configured to:
manage, for each of the plurality of blocks, a recent programming time which is a time at which data is recently programmed to a block and
erase data stored in a block for which an elapsed programming time, which is a time period from the recent programming time, is relatively long among the plurality of blocks.
2. The flash memory of claim 1 , wherein each block comprises multiple pages, and is a type of block for which the erase process is carried in units of blocks and programming is carried out in units of pages,
in relation to controlling a timing at which an erase process is carried out with respect to a block based on the recent programming time of the block, the recent programming time of the block is a time at which data is recently programmed to a last page of this block, and
the target block is an invalid block that does not comprise a valid page, which is a page identified from a physical address allocated to a logical address.
3. The flash memory of claim 1 , wherein
the controller detects an at-risk block, wherein the at-risk block is a data-programmed block for which there is a risk that reliability drops, and
in controlling a timing at which an erase process is carried out with respect to a block based on the recent programming time of this block, the controller preferentially selects an invalid block instead of the at-risk block from the multiple blocks as the target block.
4. The flash memory of claim 3 , wherein, in controlling a timing at which an erase process is carried out with respect to a block based on the recent programming time of this block, the controller is configured to:
on a condition that a number of selected blocks is less than a second value, select an invalid block as the target block and update the number of selected blocks, wherein the number of selected blocks is the number of times that invalid blocks have been selected; and
on a condition that the number of selected blocks is equal to or larger than the second value, select the at-risk block as the target block, and return the number of selected blocks to an initial value.
5. The flash memory of claim 4 , wherein the at-risk block is a block for which the number of failed bits is equal to or larger than a failed bit threshold, and
the controller identifies, from among multiple failed bit thresholds, a failed bit threshold corresponding to the elapsed programming time of the block, and in a case where the number of failed bits of this block is equal to or larger than this identified failed bit threshold, detects that this block is an at-risk block.
6. The flash memory of claim 5 , wherein the elapsed programming time includes a first time period, which is a time period from the time at which data is recently programmed to the last page, and a second time period, which is a time period from the time at which data is recently programmed to a page other than the last page, and
the elapsed programming time related to the controller detecting an at-risk block is the second time period.
7. A storage apparatus comprising:
a plurality of flash memory modules, each of the plurality of flash memory modules including a plurality of blocks, each of which is an unit of erasing data, and
a flash controller, which is coupled to the plurality of flash memory chips, configured to program data to a block and erase data from a block, wherein
the flash controller is configured to:
manage, for each of the plurality of blocks, a recent programming time which is a time at which data is recently programmed to a block and
erase data stored in a block for which an elapsed programming time, which is a time period from the recent programming time, is relatively long among the plurality of blocks.
8. The storage apparatus of claim 7 , wherein each block comprises multiple pages, and is a type of block for which the erase process is carried in units of blocks and programming is carried out in units of pages,
in relation to controlling a timing at which an erase process is carried out with respect to a block based on the recent programming time of the block, the recent programming time of the block is a time at which data is recently programmed to a last page of this block, and
the target block is an invalid block that does not comprise a valid page, which is a page identified from a physical address allocated to a logical address.
9. The storage apparatus of claim 7 , wherein
the controller detects an at-risk block, wherein the at-risk block is a data-programmed block for which there is a risk that reliability drops, and
in controlling a timing at which an erase process is carried out with respect to a block based on the recent programming time of this block, the controller preferentially selects an invalid block instead of the at-risk block from the multiple blocks as the target block.
10. The storage apparatus of claim 9 , wherein, in controlling a timing at which an erase process is carried out with respect to a block based on the recent programming time of this block, the controller is configured to:
on a condition that a number of selected blocks is less than a second value, select an invalid block as the target block and update the number of selected blocks, wherein the number of selected blocks is the number of times that invalid blocks have been selected; and
on a condition that the number of selected blocks is equal to or larger than the second value, select the at-risk block as the target block, and return the number of selected blocks to an initial value.
11. The storage apparatus of claim 10 , wherein the at-risk block is a block for which the number of failed bits is equal to or larger than a failed bit threshold, and
the controller identifies, from among multiple failed bit thresholds, a failed bit threshold corresponding to the elapsed programming time of the block, and in a case where the number of failed bits of this block is equal to or larger than this identified failed bit threshold, detects that this block is an at-risk block.
12. The storage apparatus of claim 11 , wherein the elapsed programming time includes a first time period, which is a time period from the time at which data is recently programmed to the last page, and a second time period, which is a time period from the time at which data is recently programmed to a page other than the last page, and
the elapsed programming time related to the controller detecting an at-risk block is the second time period.