Interconnectable ultrasound transducer probes and related methods and apparatus
Ultrasound devices and methods are described, including a repeatable ultrasound transducer probe having ultrasonic transducers and corresponding circuitry. The repeatable ultrasound transducer probe may be used individually or coupled with other instances of the repeatable ultrasound transducer probe to create a desired ultrasound device. The ultrasound devices may optionally be connected to various types of external devices to provide additional processing and image rendering functionality.
1. An apparatus, comprising:
a semiconductor chip including a silicon substrate, a plurality of insulating layers formed on the silicon substrate, and a metal layer between two insulating layers of the plurality of insulating layers, wherein the metal layer is connected to the silicon substrate by a conductive via passing through an insulating layer of the plurality of insulating layers, the semiconductor chip having a device surface with a width and height, the width of the device surface being at least twice as large as the height of the device surface, the metal layer having a thickness between 0.5 microns and 10 microns, wherein the width, the height, and the thickness are orthogonal to each other;
a plurality of complementary metal oxide semiconductor (CMOS) ultrasonic transducers integrated on the plurality of insulating layers, wherein at least one CMOS ultrasonic transducer of the plurality of CMOS ultrasonic transducers is disposed above the metal layer such that the metal layer is between the silicon substrate and the at least one CMOS ultrasonic transducer; and
CMOS control circuitry formed in the silicon substrate, coupled to the plurality of CMOS ultrasonic transducers by at least one conductive via passing through the insulating layer of the plurality of insulating layers and configured to control the plurality of CMOS ultrasonic transducers to support one-dimensional (1D), two-dimensional (2D), and three-dimensional (3D) ultrasound imaging,
wherein the CMOS control circuitry comprises a waveform generator coupled to the at least one CMOS ultrasonic transducer of the plurality of CMOS ultrasonic transducers through a pulser, the waveform generator configurable to generate an impulse, a continuous wave, a coded excitation, and a chirp waveform;
wherein the waveform generator comprises a plurality of registers, wherein the plurality of registers comprises a register storing a value of an initial phase, a register storing a value of an initial frequency, and a register storing a value of a frequency rate of change; and
wherein the waveform generator further comprises a plurality of comparators and a plurality of multiplexers, wherein outputs of the plurality of registers are coupled to inputs to the plurality of comparators, and wherein outputs of the plurality of comparators are coupled to inputs of the multiplexers, an output of a first multiplexer of the plurality of multiplexers being a first input to the pulser, and an output of a second multiplexer of the plurality of multiplexers being a second input to the pulser.
2. The apparatus of claim 1 , wherein the plurality of CMOS ultrasonic transducers and the CMOS control circuitry represent multiple instances of an ultrasound probe tiled on the silicon substrate.
3. The apparatus of claim 1 , wherein the CMOS control circuitry is configured to control the at least one CMOS ultrasonic transducers of the plurality of CMOS ultrasonic transducers to provide high intensity focused ultrasound (HIFU).
4. The apparatus of claim 1 , wherein the plurality of CMOS ultrasonic transducers is a first plurality of CMOS ultrasonic transducers, and wherein the apparatus further comprises a second plurality of CMOS ultrasonic transducers configured to provide high intensity focused ultrasound (HIFU).
5. The apparatus of claim 1 , wherein the pulser is a tri-level pulser.
6. The apparatus of claim 1 , wherein the pulser is configured to provide voltage pulses to the at least one CMOS ultrasonic transducer of the plurality of CMOS ultrasonic transducer having voltages between 30 Volts and 120 Volts.
7. The apparatus of claim 1 , wherein the chirp waveform is a linear frequency modulation (LFM) chirp.
8. The apparatus of claim 1 , wherein a ratio of the width of the device surface to the height of the device surface is between 5:1 and 10:1.
9. The apparatus of claim 1 , wherein the plurality of CMOS ultrasonic transducers covers more than half of the height of the device surface and less than the width of the device surface, and wherein at least a first portion of the CMOS control circuitry is formed on a peripheral region of the width of the device surface not covered by the plurality of CMOS ultrasonic transducers.
10. The apparatus of claim 1 , wherein the at least one CMOS ultrasonic transducer of the plurality of CMOS transducers comprises a membrane, and wherein the membrane is connected to the metal layer by an electrically conductive via.
11. The apparatus of claim 1 , further comprising a wiring line in the silicon substrate, wherein the at least one CMOS ultrasonic transducer of the plurality of CMOS ultrasonic transducers comprises an electrode, and wherein the metal layer is configured as an electrical shield between the electrode and the wiring line.
12. The apparatus of claim 1 , wherein the CMOS control circuitry includes a sequence processor configured to store a program controlling a sequence of operations executed by the plurality of CMOS ultrasonic transducers.
13. The apparatus of claim 1 , wherein the CMOS control circuitry comprises a sequence processor configured to operate the plurality of CMOS ultrasonic transducers semi-autonomously.
14. The apparatus of claim 1 , wherein the plurality of CMOS ultrasonic transducers are arranged in groups connected in a daisy-chain configuration by data lines.
15. The apparatus of claim 1 , further comprising time-gain compensation circuitry coupled to the plurality of CMOS ultrasonic transducers.