Microbump and sacrificial pad pattern
View Patent ↗Embodiments described herein generally relate to connections for integrated circuit (IC) dies. For example, in an embodiment an integrated circuit (IC) die is provided. The IC die includes a plurality of clusters of pads formed on a surface of the IC die, each cluster being associated with a respective circuit formed in the IC die. Each cluster includes a plurality of micropads each electrically coupled to the circuit associated with the cluster through a respective via and a sacrificial pad coupled to the circuit through the plurality of micropads, the sacrificial pad being larger than each of the micropads.
1. An integrated circuit (IC) die, comprising:
a plurality of clusters of pads, formed on a surface of the IC die, associated with a plurality of circuits formed in the IC die,
wherein each cluster of pads from among the plurality of clusters of pads comprises:
a plurality of micropads formed on the surface of the IC die, each micropad from among the plurality of micropads being physically and electrically coupled to a respective circuit from among the plurality of circuits through a respective via or trace from among a plurality of vias or traces; and
a sacrificial pad, formed on the surface of the IC die, electrically coupled to the respective circuit through the plurality of micropads, the sacrificial pad having a surface area that is different from a surface area of each micropad from among the plurality of micropads.
2. The IC die of claim 1 , wherein each micropad from among the plurality of micropads is arranged substantially equidistant from a center of the sacrificial pad.
3. The IC die of claim 1 , wherein a first distance between a first set of clusters of pads from among the plurality of clusters of pads is equal to a second distance between a second set of clusters of pads from among the plurality of clusters of pads.
4. The IC die of claim 1 , wherein a first distance between a first set of clusters of pads from among the plurality of clusters of pads is non-uniformly spaced with a second set of clusters of pads from among the plurality of clusters of pads.
5. The IC die of claim 1 , further comprising:
a trace configured to physically and electrically couple a first cluster of pads from among the plurality of clusters of pads and a second cluster of pads from among the plurality of clusters of pads.
6. The IC die of claim 5 , wherein the trace is configured to physically and electrically couple a micropad from among the plurality of micropads of the first cluster of pads and a corresponding micropad from among the plurality of micropads of the second cluster of pads.
7. The IC die of claim 1 , wherein each cluster of pads from among the plurality of clusters of pads further comprises:
a second plurality of traces, formed on the surface of the IC die, configured to physically and electrically couple the plurality of micropads and the sacrificial pad.
8. The IC die of claim 1 , wherein each cluster of pads from among the plurality of clusters of pads further comprises:
a second trace configured to physically and electrically couple a first micropad from among the plurality of micropads and a second micropad from among the plurality of micropads.
9. The IC die of claim 1 , wherein the sacrificial pad is configured to be only electrically coupled to the respective circuit.
10. The IC die of claim 1 , wherein the sacrificial pad is configured to be probed to test the respective circuit.
11. An integrated circuit (IC) die, comprising:
a plurality of micropads formed on a surface of the IC die, a first set of micropads from among the plurality of micropads being configured to form a first cluster of pads from among a plurality of clusters of pads and a second set of micropads from among the plurality of micropads being configured to form a second cluster of pads from among the plurality of clusters of pads,
wherein the first set of micropads is physically and electrically coupled to a first circuit from among a plurality of circuits formed on the surface of the IC die and the second set of micropads is physically and electrically coupled to a second circuit from among the plurality of circuits; and
a plurality of sacrificial pads formed on the surface of the IC die, a first sacrificial pad from among the plurality of sacrificial pads being physically and electrically coupled to the first set of micropads to electrically couple the first sacrificial pad to the first circuit and a second sacrificial pad from among the plurality of sacrificial pads being physically and electrically coupled to the second set of micropads to electrically couple the second sacrificial pad to the second circuit,
wherein the first sacrificial pad and the second sacrificial pad are larger than each micropad from among the first set of micropads and each micropad from among the second set of micropads, respectively.
12. The IC die of claim 11 , wherein each micropad from among first set of micropads is arranged substantially equidistant from a center of the first sacrificial pad.
13. The IC die of claim 11 , further comprising:
a trace configured to physically and electrically couple the first cluster of pads and the second cluster of pads.
14. The IC die of claim 13 , wherein the trace is configured to physically and electrically couple a first micropad from among the first set of micropads and a second micropad from among the second set, of micropads.
15. The IC die of claim 11 , further comprising:
a plurality of traces, formed on the surface of the IC die,
wherein a first set of traces from among the plurality of traces is configured to physically and electrically couple the first set of micropads and the first sacrificial pad, and
wherein a second set of traces from among the plurality of traces is configured to physically and electrically couple the second set of micropads and the second sacrificial pad.
16. The IC die of claim 11 , further comprising:
a trace configured to physically and electrically couple a first micropad from among the first set of micropads and a second micropad from among the first set of micropads.
17. The IC die of claim 11 , wherein the first set of micropads is physically and electrically coupled to the first circuit through a via.
18. The IC die of claim 11 , wherein the first set of micropads is physically and electrically coupled to the first circuit through a trace.